如何从Xilinx驱动DDS编译器IP内核

Question

我完成了Anton Potočniks' introductory guide到红色火龙果板的操作，现在我能够将SoC上运行的linux计算机的命令发送到其FPGA逻辑。

我想进一步修改项目，以便我可以控制通过红色火龙果的DAC传输的信号的相位。第一个GPIO端口的某些引脚（从7下降到1）仍未使用，因此我开始在操作系统内进行设置，并使用红色pitaya的LED确认设置是否在不干扰AntonPotočnik的“高带宽”功能的情况下平均”。

然后我将DDS_compilers'的相位偏移可编程性设置为“流”模式，以便可以使用当前控制红色pitaya的LED的位对其进行动态配置。我使用了一些切片将信号连接到AXI4-Stream Constant IP内核，该内核进而驱动DDS编译器。

不幸的是，DAC只是给了我500 mV的恒定输出。

我为DDS编译器创建了一个带有测试平台的新项目，因为综合需要很长时间，并且无法让我对正在发生的事情有太多了解。

不幸的是，DDS编译器的所有输出信号都是不确定的。

我的问题：

我在做什么错，如何继续控制DAC的相位？

EDIT1;这是我的测试台


library IEEE;                                                                                                      
use IEEE.Std_logic_1164.all;                                                                                       
use IEEE.Numeric_Std.all;                                                                                          

entity dds_compiler_0_tb is                                                                                        
end;                                                                                                               

architecture bench of dds_compiler_0_tb is                                                                         

  component dds_compiler_0                                                                                         
    PORT (                                                                                                         
      aclk : IN STD_LOGIC;                                                                                         
      s_axis_phase_tvalid : IN STD_LOGIC;                                                                          
      s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);                                                       
      m_axis_data_tvalid : OUT STD_LOGIC;                                                                          
      m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);                                                       
      aclken : IN STD_LOGIC;                                                                                       
      aresetn : IN STD_LOGIC;                                                                                      
      s_axis_phase_tlast : IN STD_LOGIC;                                                                           
      s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);                                                        
      s_axis_config_tvalid : IN STD_LOGIC;                                                                         
      s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);                                                       
      s_axis_config_tlast : IN STD_LOGIC;                                                                          
      m_axis_data_tready : IN STD_LOGIC;                                                                           
      m_axis_phase_tready : IN STD_LOGIC                                                                           
    );                                                                                                             
  end component;                                                                                                   

  signal aclk: STD_LOGIC;                                                                                          
  signal s_axis_phase_tvalid: STD_LOGIC;                                                                           
  signal s_axis_phase_tdata: STD_LOGIC_VECTOR(31 DOWNTO 0);                                                        
  signal m_axis_data_tvalid: STD_LOGIC;                                                                            
  signal m_axis_data_tdata: STD_LOGIC_VECTOR(15 DOWNTO 0) ;                                                        
  signal aclken : STD_LOGIC;                                                                                       
  signal aresetn : STD_LOGIC;                                                                                      
  signal s_axis_phase_tlast : STD_LOGIC;                                                                           
  signal s_axis_phase_tuser : STD_LOGIC_VECTOR(0 DOWNTO 0);                                                        
  signal s_axis_config_tvalid : STD_LOGIC;                                                                         
  signal s_axis_config_tdata : STD_LOGIC_VECTOR(0 DOWNTO 0);                                                       
  signal s_axis_config_tlast : STD_LOGIC;                                                                          
  signal m_axis_data_tready : STD_LOGIC;                                                                           
  signal m_axis_phase_tready : STD_LOGIC;                                                                          



  constant clock_period: time := 10 ns;                                                                            
  signal stop_the_clock: boolean;                                                                                  

begin                                                                                                              

  uut: dds_compiler_0 port map ( aclk                => aclk,                                                      
                                 s_axis_phase_tvalid => s_axis_phase_tvalid,                                       
                                 s_axis_phase_tdata  => s_axis_phase_tdata,                                        
                                 m_axis_data_tvalid  => m_axis_data_tvalid,                                        
                                 m_axis_data_tdata   => m_axis_data_tdata,                                         
                                 aclken => '1',                                                                    
                                 aresetn => '1',                                                                   
                                 s_axis_phase_tlast => '0',                                                        
                                 s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),                        
                                 s_axis_config_tvalid => '0',                                                      
                                 s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),                       
                                 s_axis_config_tlast => '0',                                                       
                                 m_axis_data_tready => '0',                                                        
                                 m_axis_phase_tready => '0'                                                        
                                 );                                                                                

  stimulus: process                                                                                                
  begin                                                                                                            

    -- Put initialisation code here                                                                                
    stop_the_clock <= false;                                                                                       
    s_axis_phase_tvalid <= '0';                                                                                    
    s_axis_phase_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(10, 32));                                                   
    aclken <= '1';                                                                                                 
    aresetn <= '1';                                                                                                
    s_axis_phase_tlast <= '0';                                                                                     
    s_axis_phase_tuser <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1));                                                     
    s_axis_config_tvalid <= '0';                                                                                   
    s_axis_config_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1));                                                    
    s_axis_config_tlast <= '0';                                                                                    

    wait for clock_period / 2;                                                                                     
    s_axis_phase_tvalid <= '1';                                                                                    
    m_axis_data_tready <= '1';                                                                                     
    m_axis_phase_tready <= '1';                                                                                    
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     
    wait for clock_period / 2;                                                                                     

    -- Put test bench stimulus code here                                                                           

    stop_the_clock <= true;                                                                                        
    wait;                                                                                                          
  end process;                                                                                                     


  clocking: process                                                                                                
  begin                                                                                                            
    while not stop_the_clock loop                                                                                  
      aclk <= '0', '1' after clock_period / 2;                                                                     
      aclk <= '0', '1' after clock_period / 2;                                                                     
      wait for clock_period;                                                                                       
    end loop;                                                                                                      
    wait;                                                                                                          
  end process;                                                                                                     

end;

IP内核的配置如下，因此不需要我提供的许多控制信号：

EDIT2;我将m_axis_data_tready => '0'形式的声明更改为m_axis_phase_tready => m_axis_phase_tready_signal。我还查看了名为dds_compiler_0.vhd的包装器文件，发现该文件将m_axis_phase_tready和m_axis_data_tready都视为输入。

我的模拟结果保持不变...

可以在这里找到我的新测试台：

library IEEE;                                                                                      
use IEEE.Std_logic_1164.all;                                                                       
use IEEE.Numeric_Std.all;                                                                          

entity dds_compiler_0_tb is                                                                        
end;                                                                                               

architecture bench of dds_compiler_0_tb is                                                         

  component dds_compiler_0                                                                         
    PORT (                                                                                         
      aclk : IN STD_LOGIC;                                                                         
      s_axis_phase_tvalid : IN STD_LOGIC;                                                          
      s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);                                       
      m_axis_data_tvalid : OUT STD_LOGIC;                                                          
      m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);                                       
      aclken : IN STD_LOGIC;                                                                       
      aresetn : IN STD_LOGIC;                                                                      
      s_axis_phase_tlast : IN STD_LOGIC;                                                           
      s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);                                        
      s_axis_config_tvalid : IN STD_LOGIC;                                                         
      s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);                                       
      s_axis_config_tlast : IN STD_LOGIC;                                                          
      m_axis_data_tready : IN STD_LOGIC;                                                           
      m_axis_phase_tready : IN STD_LOGIC                                                           
    );                                                                                             
  end component;                                                                                   

  signal aclk_signal: STD_LOGIC;                                                                   
  signal s_axis_phase_tvalid_signal: STD_LOGIC;                                                    
  signal s_axis_phase_tdata_signal: STD_LOGIC_VECTOR(31 DOWNTO 0);                                 
  signal m_axis_data_tvalid_signal: STD_LOGIC;                                                     
  signal m_axis_data_tdata_signal: STD_LOGIC_VECTOR(15 DOWNTO 0) ;                                 
  signal aclken_signal : STD_LOGIC;                                                                
  signal aresetn_signal : STD_LOGIC;                                                               
  signal s_axis_phase_tlast_signal : STD_LOGIC;                                                    
  signal s_axis_phase_tuser_signal : STD_LOGIC_VECTOR(0 DOWNTO 0);                                 
  signal s_axis_config_tvalid_signal : STD_LOGIC;                                                  
  signal s_axis_config_tdata_signal : STD_LOGIC_VECTOR(0 DOWNTO 0);                                
  signal s_axis_config_tlast_signal : STD_LOGIC;                                                   
  signal m_axis_data_tready_signal : STD_LOGIC;                                                    
  signal m_axis_phase_tready_signal : STD_LOGIC;                                                   



  constant clock_period: time := 10 ns;                                                            
  signal stop_the_clock: boolean;                                                                  

begin                                                                                              

  uut: dds_compiler_0 port map ( aclk                => aclk_signal,                               
                                 s_axis_phase_tvalid => s_axis_phase_tvalid_signal,                
                                 s_axis_phase_tdata  => s_axis_phase_tdata_signal,                 
                                 m_axis_data_tvalid  => m_axis_data_tvalid_signal,                 
                                 m_axis_data_tdata   => m_axis_data_tdata_signal,                  
                                 aclken => aclken_signal,                                          
                                 aresetn => aresetn_signal,                                        
                                 s_axis_phase_tlast => s_axis_phase_tlast_signal,                  
                                 s_axis_phase_tuser => s_axis_phase_tuser_signal,                  
                                 s_axis_config_tvalid => s_axis_config_tvalid_signal,              
                                 s_axis_config_tdata => s_axis_config_tdata_signal,                
                                 s_axis_config_tlast => s_axis_config_tlast_signal,                
                                 m_axis_data_tready => m_axis_data_tready_signal,                  
                                 m_axis_phase_tready => m_axis_phase_tready_signal                 
                                 );                                                                

  stimulus: process                                                                                
  begin                                                                                            

    -- Put initialisation code here                                                                
    stop_the_clock <= false;                                                                       
    s_axis_phase_tvalid_signal <= '0';                                                             
    s_axis_phase_tdata_signal <= STD_LOGIC_VECTOR(TO_UNSIGNED(10, 32));                            
    aclken_signal <= '1';                                                                          
    aresetn_signal <= '1';                                                                         
    s_axis_phase_tlast_signal <= '0';                                                              
    s_axis_phase_tuser_signal <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1));                              
    s_axis_config_tvalid_signal <= '0';                                                            
    s_axis_config_tdata_signal <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1));                             
    s_axis_config_tlast_signal <= '0';                                                             

    wait for clock_period / 2;                                                                     
    s_axis_phase_tvalid_signal <= '1';                                                             
    m_axis_data_tready_signal <= '1';                                                              
    m_axis_phase_tready_signal <= '1';                                                             
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     
    wait for clock_period / 2;                                                                     

    -- Put test bench stimulus code here                                                           

    stop_the_clock <= true;                                                                        
    wait;                                                                                          
  end process;                                                                                     


  clocking: process                                                                                
  begin                                                                                            
    while not stop_the_clock loop                                                                  
      aclk_signal <= '0', '1' after clock_period / 2;                                              
      aclk_signal <= '0', '1' after clock_period / 2;                                              
      wait for clock_period;                                                                       
    end loop;                                                                                      
    wait;                                                                                          
  end process;                                                                                     

end;

EDIT3：我看到包装文件（dds_compiler_0.vhd）只有五个端口：

aclk（in）
s_axis_phase_tvalid（in）
s_axis_phase_tdata（in）
m_axis_data_tvalid（输出）
和m_axis_data_tdata（输出）

因此，我从测试台上移除了所有其他信号和端口，发现我的模拟结果仍然相同。即。像m_axis_phase_tready这样的控制信号都呈现给我，即使它们不再存在于我的测试台（！）中。

也许Vivado一次又一次地给我旧的模拟结果？

Answer 1

似乎未连接m_axis_data_tready。除非声明，否则不会有数据出来。

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