在Chisel3中使用BlackBoxing后生成Verilog代码

Question

我在Chisel3中尝试BlackBox功能。每当我尝试生成Chisel的Verilog代码时，我都会收到错误.

我按照正确的步骤编写了类，类驱动程序和build.sbt。

我不确定问题出在哪里

这是我的Chisel Code

import chisel3._
import chisel3.util._
import chisel3.experimental._

class BlackBoxRealAdd extends BlackBox with HasBlackBoxInline {
  val io = IO(new Bundle() {
    val in1 = Input(UInt(64.W))
    val in2 = Input(UInt(64.W))
    val out = Output(UInt(64.W))
  })
  setInline("BlackBoxRealAdd.v",
    s"""
      |module BlackBoxRealAdd(
      |    input  [15:0] in1,
      |    input  [15:0] in2,
      |    output [15:0] out
      |);
      |always @* begin
      |  out <= (in1) + (in2));
      |end
      |endmodule
    """.stripMargin)
}


object BlackBoxRealAddDriver extends App {
  chisel3.Driver.execute(args, () => new BlackBoxRealAdd)
}

scalaVersion := "2.11.12"

resolvers ++= Seq(
  Resolver.sonatypeRepo("snapshots"),
  Resolver.sonatypeRepo("releases")
)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.1.+"

Answer 1

我已经弄清楚了。黑盒子模块不应该是最顶层的。