我不知道它是否符合Verilog-2005标准,但我设法使用«synplify pro»和«icarus verilog»编译以下代码。
integer fsm_step_number;
always @(posedge clk or posedge rst)
if(rst) begin
pc <= 8'h00;
wb_addr_o <= 8'h00;
wb_wdat_o <= 8'h00;
wb_stb_o <= 1'b0;
wb_cyc_o <= 1'b0;
wb_we_o <= 1'b0;
temt <= 1;
end
else begin
fsm_step_number=1;
case(pc)
fsm_step_number++: begin
wb_addr_o <= UART_LSR;
wb_stb_o <= 1'b1;
wb_cyc_o <= 1'b1;
wb_we_o <= 1'b0;
end
fsm_step_number++: begin
temt <= wb_rdat_i[6];
wb_stb_o <= 1'b0;
wb_cyc_o <= 1'b0;
wb_we_o <= 1'b0;
end
[...]
endcase
end
fsm_step_number整数的增量不适用于格合成程序(LSE)和Yosys。我和yosys有语法错误:
yosys> read_verilog uart_ctrl_pre.v
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `uart_ctrl_pre.v' to AST representation.
ERROR: Parser error in line uart_ctrl_pre.v:74: syntax error, unexpected TOK_INCREMENT
你知道是否有可能用Yosys做一个这样的思考(将整数增加到大小写状态)?
++
运算符在SystemVerilog中,而不是Verilog。我认为综合工具要求case(表达式)或item:
表达式列表是常量,但不允许两者都是非常量表达式。