反馈信号未定义

问题描述 投票:0回答:1

我正在研究的VHDL项目有问题。我有两个4位计数器,必须将它们链接在一起。当计数器达到8F值时,它将重置,我使用2个解码器进行了处理。所以问题是,它不起作用。就像反馈信号始终没有被定义一样。但是在4位计数器中定义了它。有任何想法吗 ?预先感谢您的回答!

这里是Active-HDL从框图生成的代码。


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;


entity counter8bit is
  port(
       C : in STD_LOGIC;
       EC : in STD_LOGIC;
       EL : in STD_LOGIC;
       EP : in STD_LOGIC;
       R : in STD_LOGIC;
       Y0 : out STD_LOGIC;
       Y1 : out STD_LOGIC;
       Y2 : out STD_LOGIC;
       Y3 : out STD_LOGIC;
       Y4 : out STD_LOGIC;
       Y5 : out STD_LOGIC;
       Y6 : out STD_LOGIC;
       Y7 : out STD_LOGIC
  );
end counter8bit;

architecture counter8bit of counter8bit is

---- Component declarations -----

component counter4bit
  port (
       C : in STD_LOGIC;
       D0 : in STD_LOGIC;
       D1 : in STD_LOGIC;
       D2 : in STD_LOGIC;
       D3 : in STD_LOGIC;
       EC : in STD_LOGIC;
       EL : in STD_LOGIC;
       EP : in STD_LOGIC;
       R : in STD_LOGIC;
       P : out STD_LOGIC;
       Q0 : out STD_LOGIC;
       Q1 : out STD_LOGIC;
       Q2 : out STD_LOGIC;
       Q3 : out STD_LOGIC
  );
end component;
component decoder1
  port (
       CS1 : in STD_LOGIC;
       CS2 : in STD_LOGIC;
       D0 : in STD_LOGIC;
       D1 : in STD_LOGIC;
       D2 : in STD_LOGIC;
       D3 : in STD_LOGIC;
       Q0 : out STD_LOGIC;
       Q1 : out STD_LOGIC;
       Q10 : out STD_LOGIC;
       Q11 : out STD_LOGIC;
       Q12 : out STD_LOGIC;
       Q13 : out STD_LOGIC;
       Q14 : out STD_LOGIC;
       Q15 : out STD_LOGIC;
       Q2 : out STD_LOGIC;
       Q3 : out STD_LOGIC;
       Q4 : out STD_LOGIC;
       Q5 : out STD_LOGIC;
       Q6 : out STD_LOGIC;
       Q7 : out STD_LOGIC;
       Q8 : out STD_LOGIC;
       Q9 : out STD_LOGIC
  );
end component;
component decoderL
  port (
       CS1 : in STD_LOGIC;
       CS2 : in STD_LOGIC;
       D0 : in STD_LOGIC;
       D1 : in STD_LOGIC;
       D2 : in STD_LOGIC;
       D3 : in STD_LOGIC;
       Q0 : out STD_LOGIC;
       Q1 : out STD_LOGIC;
       Q10 : out STD_LOGIC;
       Q11 : out STD_LOGIC;
       Q12 : out STD_LOGIC;
       Q13 : out STD_LOGIC;
       Q14 : out STD_LOGIC;
       Q15 : out STD_LOGIC;
       Q2 : out STD_LOGIC;
       Q3 : out STD_LOGIC;
       Q4 : out STD_LOGIC;
       Q5 : out STD_LOGIC;
       Q6 : out STD_LOGIC;
       Q7 : out STD_LOGIC;
       Q8 : out STD_LOGIC;
       Q9 : out STD_LOGIC
  );
end component;

----     Constants     -----
constant GND_CONSTANT   : STD_LOGIC := '0';

---- Signal declarations used on the diagram ----

signal GND : STD_LOGIC;
signal NET1170 : STD_LOGIC;
signal NET288 : STD_LOGIC;
signal NET297 : STD_LOGIC;
signal NET515 : STD_LOGIC;
signal NET520 : STD_LOGIC;
signal NET525 : STD_LOGIC;
signal NET530 : STD_LOGIC;
signal NET535 : STD_LOGIC;
signal NET540 : STD_LOGIC;
signal NET545 : STD_LOGIC;
signal NET550 : STD_LOGIC;
signal NET555 : STD_LOGIC;
signal NET560 : STD_LOGIC;
signal NET565 : STD_LOGIC;
signal NET570 : STD_LOGIC;
signal NET575 : STD_LOGIC;
signal NET580 : STD_LOGIC;
signal NET585 : STD_LOGIC;
signal NET590 : STD_LOGIC;
signal NET595 : STD_LOGIC;
signal NET598 : STD_LOGIC;
signal NET602 : STD_LOGIC;
signal NET606 : STD_LOGIC;
signal NET610 : STD_LOGIC;
signal NET614 : STD_LOGIC;
signal NET618 : STD_LOGIC;
signal NET622 : STD_LOGIC;
signal NET647 : STD_LOGIC;
signal NET651 : STD_LOGIC;
signal NET655 : STD_LOGIC;
signal NET659 : STD_LOGIC;
signal NET663 : STD_LOGIC;
signal NET667 : STD_LOGIC;
signal Q0 : STD_LOGIC;
signal Q1 : STD_LOGIC;
signal Q2 : STD_LOGIC;
signal Q3 : STD_LOGIC;
signal Q4 : STD_LOGIC;
signal Q5 : STD_LOGIC;
signal Q6 : STD_LOGIC;
signal Q7 : STD_LOGIC;
signal Q8 : STD_LOGIC;
signal Q9 : STD_LOGIC;

begin

----  Component instantiations  ----

U1 : counter4bit
  port map(
       C => C,
       D0 => GND,
       D1 => GND,
       D2 => GND,
       D3 => GND,
       EC => EC,
       EL => EL,
       EP => EP,
       P => Q8,
       Q0 => Q0,
       Q1 => Q1,
       Q2 => Q2,
       Q3 => Q3,
       R => Q9
  );

U2 : counter4bit
  port map(
       C => C,
       D0 => GND,
       D1 => GND,
       D2 => GND,
       D3 => GND,
       EC => EC,
       EL => EL,
       EP => Q8,
       P => NET1170,
       Q0 => Q4,
       Q1 => Q5,
       Q2 => Q6,
       Q3 => Q7,
       R => Q9
  );

Q9 <= NET297 and NET288;

U7 : decoder1
  port map(
       CS1 => R,
       CS2 => GND,
       D0 => Q4,
       D1 => Q5,
       D2 => Q6,
       D3 => Q7,
       Q0 => NET585,
       Q1 => NET580,
       Q10 => NET540,
       Q11 => NET535,
       Q12 => NET530,
       Q13 => NET525,
       Q14 => NET520,
       Q15 => NET515,
       Q2 => NET575,
       Q3 => NET570,
       Q4 => NET565,
       Q5 => NET560,
       Q6 => NET555,
       Q7 => NET550,
       Q8 => NET288,
       Q9 => NET545
  );

U8 : decoderL
  port map(
       CS1 => R,
       CS2 => GND,
       D0 => Q0,
       D1 => Q1,
       D2 => Q2,
       D3 => Q3,
       Q0 => NET667,
       Q1 => NET663,
       Q10 => NET606,
       Q11 => NET602,
       Q12 => NET598,
       Q13 => NET595,
       Q14 => NET590,
       Q15 => NET297,
       Q2 => NET659,
       Q3 => NET655,
       Q4 => NET651,
       Q5 => NET647,
       Q6 => NET622,
       Q7 => NET618,
       Q8 => NET614,
       Q9 => NET610
  );


---- Power , ground assignment ----

GND <= GND_CONSTANT;

---- Terminal assignment ----

    -- Output\buffer terminals
    Y0 <= Q0;
    Y1 <= Q1;
    Y2 <= Q2;
    Y3 <= Q3;
    Y4 <= Q4;
    Y5 <= Q5;
    Y6 <= Q6;
    Y7 <= Q7;


end counter8bit;

反码(有点复杂,但是我们的老师想要这样):

library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use IEEE.std_logic_unsigned.all;  
use ieee.numeric_std.all;

entity counter4bit is
     port(
         EP : in STD_LOGIC;
         EC : in STD_LOGIC;
         C : in STD_LOGIC;
         D0 : in STD_LOGIC;
         D1 : in STD_LOGIC;
         D2 : in STD_LOGIC;
         D3 : in STD_LOGIC;
         EL : in STD_LOGIC;
         R : in STD_LOGIC;
         Q0 : out STD_LOGIC;
         Q1 : out STD_LOGIC;
         Q2 : out STD_LOGIC;
         Q3 : out STD_LOGIC;
         P : out STD_LOGIC
         );
end counter4bit;

architecture counter4bit of counter4bit is   

signal countVector : std_logic_vector(3 downto 0);

begin                    
    process(C, EP, EL, EC, R)           
    variable count : integer := 0;
    begin               
        if (R = '0') then   -- Reset counter
            Q0 <= '0';
            Q1 <= '0';
            Q2 <= '0';
            Q3 <= '0';  
            P <= '0';
        elsif (R = '1') then 
            if (C'event and C = '1') then      
                if (EL = '0') then
                    Q0 <= D0;
                    Q1 <= D1;
                    Q2 <= D2;
                    Q3 <= D3;
                elsif (EL = '1') then 
                    if (EC = '1' and EP = '1') then
                        count := count + 1;          
                    elsif (EC = '0' or EP = '0') then     
                        --keep output
                    end if;
                end if;
            end if;
        end if;       

        if (count = 16) then
            count := 0;
            P <= '1';        
        end if;

        countVector <= std_logic_vector(to_unsigned(count, 4));    
        Q0 <= countVector(0);              
        Q1 <= countVector(1);
        Q2 <= countVector(2);
        Q3 <= countVector(3);

    end process;                

end counter4bit;

screenshot of block diagram

vhdl fpga
1个回答
-1
投票
  • EP, EL, EC不必在灵敏度列表中
  • elsif (R = '1') then应该只是别的(或者直接是带时钟的elsif),否则在合成时会遇到问题。与elsif (EL = '1') then相同
  • elsif (EC = '0' or EP = '0') then无用
  • 您绝不会在复位以外的任何地方复位P(R ='1')。您可能希望在时钟部分使用默认的P<='0'
  • if (count = 16) then ...应该被计时,或者您可以在增量延迟之后设置P(模拟步骤,这可能会使您用C计时的所有事情弄乱。因此,将其移动到count := count + 1;的下面,没有上一点,您只会得到您永远不会看到的故障...
  • 重设不会重设计数!?真奇怪...
  • EL为低电平有效,EC和EP为高电平有效。那应该包括在他们的名字里...

抱歉,我没有使用2个计数器检查代码

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