如何像在 Verilog 实例数组中那样实例化 VHDL 实例数组?

问题描述 投票:0回答:1

我有一个实体

entity adder is
  port (
    a, b : in  std_logic;
    sum  : out std_logic
  );
end entity adder;
architecture behav of adder is
begin
  sum <= a xor b;
end architecture behav;

如何像我们在 Verilog 中那样创建该实体的数组实例化?我试图创建一种实体类型,它显示无法创建实体类型。

vhdl
1个回答
0
投票

您将需要同一实体的多个实例和矢量信号以简化编码。让我们从具有 3 个实体的第一个简单案例开始:

#signals for entities
signal a0 : std_logic;
signal a1 : std_logic;
signal a2 : std_logic;

signal b0 : std_logic;
signal b1 : std_logic;
signal b2 : std_logic;

signal out0 : std_logic;
signal out1 : std_logic;
signal out2 : std_logic;

-- Entity instantiation

adder_0 : adder 
   port map(
        a => a0,
        b => b0,
        out => out0
  );


adder_1 : adder 
   port map(
        a => a1,
        b => b1,
        out => out1
  );


adder_2 : adder 
   port map(
        a => a2,
        b => b2,
        out => out2
  );

然而这并不紧凑,有很多重复,如果实例是 100 个而不是 3 个,几乎无法编写。幸运的是 VHDL 有 for 循环和数组:

-- Array type
type t_adder_array is array(2 downto 0) of std_logic;
signal a : t_adder_array;
signal b : t_adder_array;
signal out : t_adder_array;

-- or use a std_logic_vector because in your case the base type is just std_logic
-- please note that if the base type of the array is anything more complex, like a record, 
-- you need to define it with the array syntax.
signal a : std_logic_vector(2 downto 0);
signal b : std_logic_vector(2 downto 0);
signal out : std_logic_vector(2 downto 0);

-- The we instantiate all the entities in a for loop

gen_adders: for k in 0 to 2 generate
   adder_k : adder 
      port map(
        a => a(k),
        b => b(k),
        out => out(k)
  );
end generate;


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