如何修复VHDL中的“未知的正式标识符”错误

问题描述 投票：-2回答：1

我的VHDL代码出错了。我正在使用ModelSim软件。

我是新手。发布了类似的问题，但这并没有解决我的问题。端口映射中的实际问题。我为中间线分配了一个信号，但它仍然显示未知的正式标识符。这就是我在这里的原因。

-- Insert library and use clauses
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

-- Begin entity declaration for top-level "mult8x8"
ENTITY mult8x8 IS
-- Begin port declartion
PORT (
    -- Declare control inputs "clk", "start" and "reset_a"
    clk, start, reset_a : IN STD_LOGIC;

    -- Declare data inputs "dataa" and "datab"
    dataa, datab : IN UNSIGNED(7 DOWNTO 0);

    -- Declare multiplier output "product8x8_out"
    product8x8_out : OUT UNSIGNED(15 DOWNTO 0);

    -- Declare seven segment display outputs
    seg_a, seg_b, seg_c, seg_d, seg_e, seg_f, seg_g, done_flag : OUT 
    STD_LOGIC
);

   -- End entity
   END ENTITY mult8x8;

   ARCHITECTURE logic OF mult8x8 IS

-- Declare all lower level components
COMPONENT adder
    PORT (  
        dataa, datab : IN UNSIGNED (15 DOWNTO 0);
        sum : OUT UNSIGNED (15 DOWNTO 0)
          );
END COMPONENT adder;

 ---##################################################  
 -- complete component instantiations
 -- the components were created in the prior labs
 --- ############### ----

COMPONENT mult4x4
    PORT(
        dataa, datab : IN UNSIGNED(3 DOWNTO 0);
        product : OUT UNSIGNED(7 DOWNTO 0)
        );
END COMPONENT mult4x4;

COMPONENT mux4
    PORT(
        mux_in_a, mux_in_b: IN UNSIGNED(3 DOWNTO 0);
        mux_sel : IN STD_LOGIC;
        mux_out : OUT UNSIGNED(3 DOWNTO 0)
        );
END COMPONENT mux4;

COMPONENT shifter
        Port ( 
            input: IN UNSIGNED (7 DOWNTO 0);
        shift_cntrl : IN UNSIGNED (1 DOWNTO 0);
        shift_out : OUT UNSIGNED (15 DOWNTO 0)
        );
END COMPONENT shifter;

COMPONENT counter
    PORT (
        clk, aclr_n : IN STD_LOGIC;
        count_out : OUT UNSIGNED (1 DOWNTO 0)
    );
END COMPONENT counter;

COMPONENT mult_control
    PORT (
        clk, reset_a, start : IN STD_LOGIC;
        count : IN UNSIGNED (1 DOWNTO 0);
        input_sel, shift_sel : OUT UNSIGNED(1 DOWNTO 0);
        state_out : OUT UNSIGNED(2 DOWNTO 0);
        done, clk_ena, sclr_n : OUT STD_LOGIC
    );
END COMPONENT mult_control; 

COMPONENT seven_segment_cntrl
    Port ( input : in  UNSIGNED (2 downto 0);
               seg_a : out  STD_LOGIC;
               seg_b : out  STD_LOGIC;
               seg_c : out  STD_LOGIC;
               seg_d : out  STD_LOGIC;
               seg_e : out  STD_LOGIC;
               seg_f : out  STD_LOGIC;
               seg_g : out  STD_LOGIC);
END COMPONENT seven_segment_cntrl;

COMPONENT reg16
    Port(
        clk, clk_ena, sclr_n : IN STD_LOGIC;
        datain: IN UNSIGNED (15 DOWNTO 0);
        reg_out : OUT UNSIGNED (15 DOWNTO 0)
        );
END COMPONENT  reg16; 
--- ############### ----


-- Declare internal signals to use as wires to connect blocks
-- used these signals to connect up all the components
-- you should not need anymore signals
---
SIGNAL aout, bout : UNSIGNED(3 DOWNTO 0);
SIGNAL product : UNSIGNED(7 DOWNTO 0);
SIGNAL shift_out, sum, product8x8 : UNSIGNED(15 DOWNTO 0);
SIGNAL count, shift : UNSIGNED(1 DOWNTO 0);
SIGNAL state_out : UNSIGNED(2 DOWNTO 0);
SIGNAL clk_ena, sclr_n, start_n : std_logic;
SIGNAL sel : UNSIGNED(1 DOWNTO 0);

BEGIN
-- Start SIGNAL requires inversion before connecting to counter
start_n <= not(start);

-- Connect blocks per schematic in the lab manual
-- this port map is completed
u1: mux4 PORT MAP (mux_in_a => dataa(3 DOWNTO 0), 
                   mux_in_b => dataa(7 DOWNTO 4), 
                   mux_sel => sel(0),
                   mux_out => aout(3 DOWNTO 0));


u2: mux4 PORT MAP (mux_in_a => dataa(3 DOWNTO 0), 
                   mux_in_b => dataa(7 DOWNTO 4), 
                   mux_sel => sel(0),
                   mux_out => aout(3 DOWNTO 0));

u3: mult4x4 PORT MAP (aout => dataa (3 DOWNTO 0),
              bout => datab (3 DOWNTO 0),
                   product => product(7 DOWNTO 0));

u4: shifter PORT MAP (product => input (7 DOWNTO 0),
                shift => shift_cntrl (1 DOWNTO 0),
                shift_out => shift_out (15 DOWNTO 0));

u5: counter PORT MAP (clk => clk, 
              start => aclr_n,
                count => count_out (1 DOWNTO 0));

u6: mult_control PORT MAP (clk => clk, 
               reset_a => reset_a, 
               start => start,
               count => count (1 DOWNTO 0),
                sel => input_sel (1 DOWNTO 0), 
                shift => shift_sel (1 DOWNTO 0),
                state_out => state_out (2 DOWNTO 0),
                done => done, 
                clk_ena => clk_ena, 
                sclr_n => sclr_n);

u7: reg16 PORT MAP (clk => clk, 
            clk_era => clk_ena, 
            sclr_n => sclr_n,
            sum => datain (15 DOWNTO 0),
                product8x8 => reg_out (15 DOWNTO 0));


u8: adder PORT MAP (shift_out => dataa (15 DOWNTO 0), 
            product8x8 => datab (15 DOWNTO 0),
                sum => sum (15 DOWNTO 0));



u9: seven_segment_cntrl PORT MAP (state_out => input (2 downto 0),
                    seg_a => seg_a,
                    seg_b => seg_b,
                    seg_c => seg_c,
                    seg_d => seg_d,
                    seg_e => seg_e,
                    seg_f => seg_f,
                    seg_g => seg_g);



product8x8_out <= product8x8;

-- End architecture
END ARCHITECTURE logic;

当我卷起它时，它显示出这些错误。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（151）:( vcom-1484）未知的正式标识符“aout”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（152）:( vcom-1484）未知的正式标识符“bout”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（155）:( vcom-1136）未知标识符“input”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（156）:( vcom-1136）未知标识符“shift_cntrl”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（155）:( vcom-1484）未知的正式标识符“product”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（156）:( vcom-1484）未知的正式标识符“shift”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(160):(vcom-1136）未知标识符“aclr_n”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（161）:( vcom-1136）未知标识符“count_out”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(160):(vcom-1484）未知的正式标识符“start”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（161）:( vcom-1484）未知的正式标识符“count”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（167）:( vcom-1136）未知标识符“input_sel”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（168）:( vcom-1136）未知标识符“shift_sel”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（170）:( vcom-1136）未知标识符“已完成”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（167）:( vcom-1484）未知的正式标识符“sel”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(168):(vcom-1484）未知的正式标识符“shift”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（177）:( vcom-1136）未知标识符“datain”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（178）:( vcom-1136）未知标识符“reg_out”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（175）:( vcom-1484）未知的正式标识符“clk_era”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(177）:( vcom-1484）未知的正式标识符“sum”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（178）:( vcom-1484）未知的正式标识符“product8x8”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（181）:( vcom-1484）未知的正式标识符“shift_out”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（182）:( vcom-1484）未知的正式标识符“product8x8”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（187）:( vcom-1136）未知标识符“input”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd（187）:( vcom-1484）未知的正式标识符“state_out”。

**错误：E：/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(201):VDLDL编译器退出

请帮我解决错误。我会非常感谢你，这对我来说真的很感激。

vhdl hdl modelsim
1个回答
0
投票

大多数实例化的映射都是错误的。组件端口应位于LHS上，并带有您在RHS上映射的信号。

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