这是在 MPLAB X 中使用编译器 XC8 编写的代码:
PROCESSOR 18F2550
#include <xc.h>
; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
CONFIG USBDIV = 1 ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)
; CONFIG1H
CONFIG FOSC = HS ; Oscillator Selection bits (HS oscillator (HS))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOR = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG BORV = 3 ; Brown-out Reset Voltage bits (Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable bit (USB voltage regulator disabled)
; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = OFF ; CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = OFF ; MCLR Pin Enable bit (RE3 input pin enabled; MCLR pin disabled)
; CONFIG4L
CONFIG STVREN = OFF ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
// config statements shou
#define _XTAL_FREQ 4000000
PSECT resetVect, class=CODE, delta=2
resetVect:
PAGESEL main
goto main
PSECT code, delta=2
main:
SETF 0f93h ;0f93h is TRISB
BCF 0f93h, 2
BSF 0f93h, 1
loop:
BTFSS 0f81h, 1 ;0f81h is PORTB
goto SET_RB2:
BCF 0f81h, 2
goto loop
SET_RB2:
BSF 0f81h, 2
goto loop
goto main
END resetVect
对应的Proteus仿真是这样的:
当我按下按钮时,RB1 接地,当接地时,RB2 应设置为高电平并使 LED 打开,但这不起作用。注意,C 中的代码运行良好:
#include <xc.h>
#pragma config OSC=HS
#pragma config LVP=OFF
#pragma config PBADEN=OFF
#pragma config WDT=OFF
#pragma config MCLRE=OFF
#define _XTAL_FREQ 4000000
void main(void) {
TRISB = 0xFF;
TRISB &= ~(1 << 2);
TRISB |= 1 << 1;
while(1) {
if(PORTB & (1<<1)){
PORTB &= ~(1 << 2);
}
else {
PORTB |= 1 << 2;
}
}
return;
}
我对 Proteus 工具一无所知,但是如果没有晶体连接到振荡器引脚,模拟如何工作?
这就是我为 Microchip pic-as 工具链编写应用程序的方式:
; File: main.S
; Target: PIC18F2550
; Author: dan1138
; Date: 2023-DEC-07
; Compiler: pic-as(v2.45)
; IDE: MPLABX v6.15
;
; Description:
;
;
; Add to the MPLABX project Additional options:
; -Wa,-a -Wl,-presetVec=0h,-phi_int_vec=08h,-plo_int_vec=18h
;
; PIC18F2550
; +------------:_:------------+
; VPP -> 1 : RE3/MCLRn/VPP PGD/RB7 : 28 <> PGD
; -> 2 : RA0/AN0 PGC/RB6 : 27 <> PGC
; <> 3 : RA1/AN1 PGM/RB5 : 26 <>
; <> 4 : RA2/AN2 AN11/RB4 : 25 <>
; <> 5 : RA3/AN3 AN9/RB3 : 24 <>
; <> 6 : RA4/C1OUT AN8/RB2 : 23 <>
; <> 7 : RA5/AN4 AN10/RB1 : 22 <>
; GND <> 8 : VSS AN12/RB0 : 21 <>
; 20MHz <> 9 : RA7/OSC1 VDD : 20 <- 5v0
; 20MHz <> 10 : RA6/OSC2 VSS : 19 <- GND
; 32.768KHz <> 11 : RC0/SOSCO RX/DT/RC7 : 18 <>
; 32.768KHz <> 12 : RC1/SOSCI TX/CK/RC6 : 17 <>
; <> 13 : RC2/CCP1 D+/RC5 : 16 <-
; <> 14 : VUSB D-/RC4 : 15 <-
; +---------------------------:
; DIP-28
; Note:
; RC4,RC5 can only be used as digital inputs when the USB transceiver is not used.
;
processor 18F2550
pagewidth 132
radix dec
; PIC18F2550 Configuration Bit Settings
; Assembly source line config statements
; CONFIG1L
CONFIG PLLDIV = 5 ; PLL Prescaler Selection bits (Divide by 5 (20 MHz oscillator input))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
CONFIG USBDIV = 2 ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)
; CONFIG1H
CONFIG FOSC = HSPLL_HS ; Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOR = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG BORV = 3 ; Brown-out Reset Voltage bits (Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable bit (USB voltage regulator disabled)
; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
;
; Specify the System clock frequency in Hz that this code must setuop
;
#define FSYS 48000000
;
; Specify the Peripheral clock frequency in Hz
;
#define FCY (FSYS/4)
;
; Include device specific definitions for Special Function Registers
;
#include <xc.inc>
;
; Preprocessor macro to help with LFSR opcode
;
#define FSR(x) (x)
;
psect resetVec,reloc=2,class=CODE,delta=1
;
resetVec:
clrf TBLPTRU,c
goto Start
;
psect hi_int_vec,reloc=2,class=CODE,delta=1
;
goto HighIsrHandler
;
psect LowIsr_data,class=COMRAM,space=1,delta=1,lowdata,noexec
;
global WREG_save,STATUS_save,BSR_save
;
WREG_save: ds 1
STATUS_save: ds 1
BSR_save: ds 1
;
psect lo_int_vec,reloc=2,class=CODE,delta=1
;
LowIsrVec:
movff WREG,WREG_save
movff STATUS,STATUS_save
movff BSR,BSR_save
;
LowIsrHandler:
;
movff BSR_save,BSR
movff STATUS_save,STATUS
movff WREG_save,WREG
retfie 0
;
psect HighIsr_code,reloc=2,class=CODE,delta=1
;
HighIsrHandler:
retfie 1
;
psect start_code,reloc=2,class=CODE,delta=1
;
Start:
bcf INTCON,INTCON_GIEH_POSITION,0 ; Disable all interrupts
bcf INTCON,INTCON_GIEL_POSITION,0
bsf RCON,RCON_IPEN_POSITION,0 ; Enable interrupt priority
;
movlw 0x00 ; Set primary oscillator as system clock source
movwf OSCCON,c ;
;
movlw 0x0F ; Setup all GPIO pins
movwf ADCON1,c ; for digital I/O
;
goto main
;
;
psect main_code,reloc=2,class=CODE,delta=1
;
main:
setf TRISB,c
bcf TRISB,TRISB_TRISB2_POSITION,c
bsf TRISB,TRISB_TRISB1_POSITION,c
;
AppLoop:
btfss PORTB,PORTB_RB1_POSITION,c
bra SET_RB2
bcf LATB,LATB_LATB2_POSITION,c
bra AppLoop
SET_RB2:
bsf LATB,LATB_LATB2_POSITION,c
goto AppLoop
;
END resetVec