尝试使用多个组件，形成组合循环

Question

我创建了每个模块和一个测试台。每个都完全按照模拟器中的规定执行。但是，当我尝试合成时，出现错误“ 2170-Unit VgaTest：以下信号形成组合循环：U1 / Madd_divider_lut <1>”，然后执行映射过程，从顶级模块中删除每个信号（消息701）这使我的设备没有任何输出（已通过示波器确认）

我不明白为什么它可以模拟并正常工作，但是可以做到这一点。任何建议或信息，将不胜感激。（在spartan6上使用具有100Mhz时钟的mimas v2，是的，我知道时钟是25.000 mhz而不是25.175）

ClockGen：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity ClockGen is
    Port (    clk : in  STD_LOGIC;
               rst : in  STD_LOGIC;
           clkout : out STD_LOGIC);
end ClockGen;

architecture Behavioral of ClockGen is
    signal divider : std_logic_vector(3 downto 0) := (others => '0');
begin
    process(clk, rst)
    begin
        if (rst = '1') then
            divider <= "0000";
        else
            divider <= divider + '1';
        end if;
    end process;

    clkout <= divider(3);
end Behavioral;

VgaController：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vgaController is
    Port(
          clk: in std_logic;    -- pixel clock (25.175Mhz)
        hsync: out std_logic;
        vsync: out std_logic;
            r: out std_logic_vector(3 downto 0);
            g: out std_logic_vector(3 downto 0);
            b: out std_logic_vector(2 downto 0)
    );
end vgaController;

architecture Behavioral of vgaController is
    -- horizontal timing(line)
    constant hva: integer := 640;   -- visible area
    constant hfp: integer := 16;    -- front porch
    constant hsp: integer := 96;    -- sync pulse
    constant hbp: integer := 48;    -- back porch

    -- vertical timing
    constant vva: integer := 480; -- visible area
    constant vfp: integer := 10;    -- front porch
    constant vsp: integer := 2; -- sync pulse
    constant vbp: integer := 32;    -- back porch

    signal HPOS: integer range 0 to 800 := 0;
    signal VPOS: integer range 0 to 525 := 0;
begin
    process (clk)
    begin
        if (rising_edge(clk)) then
            -- update the position counters
            if (HPOS < (hva+hfp+hsp+hbp)) then  -- are we within the horizontal area?
                HPOS <= HPOS + 1;
            else
                HPOS <= 0;
                if (VPOS < (vva+vfp+vsp+vbp)) then  -- are we within vertical area?
                    VPOS <= VPOS + 1;
                else
                    VPOS <= 0;
                end if;
            end if;

            -- update the sync signals
            if (HPOS > (hva+hfp) and HPOS < (hva+hfp+hsp)) then -- horiz sync
                hsync <= '0';
            else
                hsync <= '1';
            end if;

            if (VPOS > (vva+vfp) and VPOS < (vva+vfp+vsp)) then -- vertical sync
                vsync <= '0';
            else
                vsync <= '1';
            end if;

            -- TEMP -- SET OUR PIXELS (this will be replaced with actual driver code later)
            if ((HPOS > hva) or (VPOS > vva)) then
                -- blank signal
                R <= (others => '0');
                G <= (others => '0');
                B <= (others => '0');
            else
                -- blue background
                R <= (others => '0');
                G <= (others => '0');
                B <= (others => '1');

                -- white cross hair
                if ((HPOS > 475 and HPOS < 485) or (VPOS > 280 and VPOS < 290)) then
                    R <= (others => '1');
                    G <= (others => '1');
                    B <= (others => '1');
                end if;
            end if;
        end if;
    end process;
end Behavioral;

和VgaTest（最上方的模块）：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity VgaTest is
    Port(
          clk: in std_logic;
        HSYNC: out std_logic;
        VSYNC: out std_logic;
            r: out std_logic_vector(3 downto 0);
            g: out std_logic_vector(3 downto 0);
            b: out std_logic_vector(2 downto 0)
    );
end VgaTest;

architecture Behavioral of VgaTest is
    component ClockGen
    Port(
         clk : IN  std_logic;
         rst : IN  std_logic;
         clkout : OUT  std_logic
        );
    end component;

    component vgaController
    Port(
         clk : IN  std_logic;
         hsync : OUT  std_logic;
         vsync : OUT  std_logic;
         r : OUT  std_logic_vector(3 downto 0);
         g : OUT  std_logic_vector(3 downto 0);
         b : OUT  std_logic_vector(2 downto 0)
        );
    end component;

     signal clktmp: std_logic;

     signal out_hsync: std_logic := '0';
     signal out_vsync: std_logic := '0';

     signal out_r: std_logic_vector(3 downto 0);
     signal out_g: std_logic_vector(3 downto 0);
     signal out_b: std_logic_vector(2 downto 0);

begin

   U1: ClockGen Port map (
          clk => clk,
          rst => '0',           -- reset is not being used, so hardwire it low
          clkout => clktmp
       );

   U2: vgaController Port map (
          clk => clktmp,
          hsync => out_hsync,
          vsync => out_vsync,
          r => out_r,
          g => out_g,
          b => out_b
        );

    HSYNC <= out_hsync;
    VSYNC <= out_vsync;
    r <= out_r;
    g <= out_g;
    b <= out_b;
end Behavioral;

我真的在想这可能是一个新手问题，但我似乎无法弄清楚原因。

已编辑，删除了与另一个问题的相似性。我将标记为已解决，但是指出的问题是我的clockgen进程实际上没有被计时。通过更改为具有

elsif(rising_edge(clk)) then
 ...

解决了合成器的投诉。尚未在真实硬件上进行测试，但我认为它仍然会失败。

Answer 1

根据user1155120，问题是时钟。它会综合整个网络，因为它从未产生过时钟。这是解决方法

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity ClockGen is
    Port (    clk : in  STD_LOGIC;
               rst : in  STD_LOGIC;
           clkout : out STD_LOGIC);
end ClockGen;

architecture Behavioral of ClockGen is
    signal divider : std_logic_vector(3 downto 0) := (others => '0');
begin
    process(clk, rst)
    begin
        if (rst = '1') then
            divider <= "0000";
        elsif (rising_edge(clk)) then
            divider <= divider + '1';
        end if;
    end process;

    clkout <= divider(3);
end Behavioral;

使用此按钮，如果显示器可以支持25Mhz平面，它将显示良好。时钟被PLL设置所代替，可以精确地给我25.175，使其可以在任何显示器上工作（至少到目前为止我已经尝试过）]