我在这里有我的代码,但是当我运行我的TB时,我遇到的问题是,当我离开左='1'并且时钟又有另一个上升沿时,我的移位无法进行。
这里的目的是制作一个左右平行移位寄存器。寄存器必须在时钟的每个上升沿更新。当le高时,它加载信息;当le高时,它应该左移。如果右边高,则应该做右边的循环移位。
table explaining function of register我该怎么办?
---------------------------------------------------------
-- Description:
-- An n-bit register (parallel in and out) with left and right shift
-- functionality (circular).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lr_shift_par_load is
generic(
C_REG_WIDTH : natural := 8
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
left : in STD_LOGIC;
right : in STD_LOGIC;
le : in STD_LOGIC;
par_in : in STD_LOGIC_VECTOR(C_REG_WIDTH-1 downto 0);
par_out : out STD_LOGIC_VECTOR(C_REG_WIDTH-1 downto 0)
);
end lr_shift_par_load;
architecture Behavioral of lr_shift_par_load is
signal reg_i : std_logic_vector(C_REG_WIDTH-1 downto 0) := (others=>'0');
begin
-- TODO: Write a process that implements the correct behaviour for reg_i.
-- This should be a good refresher of your knowledge of last year.
process(clk,reset)
begin
if(reset = '1')then
reg_i <= (others=>'0');
end if;
if(rising_edge(clk)) then
if(le ='1') then
-- load
reg_i <= par_in;
elsif(le ='0' and left ='1')then
-- shift left
reg_i <= par_in(C_REG_WIDTH-2 downto 0) & par_in(C_REG_WIDTH-1);
elsif(le ='0' and left ='0'and right ='1')then
-- shift right
reg_i <= par_in(0) & par_in(C_REG_WIDTH-1 downto 1);
elsif(le ='0' and left ='0'and right ='0')then
--hold
reg_i <= par_in;
end if;
end if;
end process;
par_out <= reg_i;
end Behavioral;
移位时,使用输入向量'par_in'。您可能要使用移位寄存器本身:“ reg_i”。
而且您的条件也不必要复杂。
if(le ='1') then
-- load
reg_i <= par_in;
elsif(le ='0' ... << Why are you testing for this?
If "le" was not zero it would never get here
but get handled in the first 'if'.
这里相同:
(le ='0' and left ='0'and right ='1') then
(le ='0' and left ='0'
是多余的。