Verilog 中的时间变量积分器

Question

我正在尝试用 Verilog 编写一个集成模块，它可以改变集成周期的持续时间。编译没有错误，信号的数据寄存器实际上存储了信号，但积分总线保持在 0。

积分是在for循环中计算的，如下所示

for (i = 0; i < duration; i = i + 1) integral = integral + memory[i];

integral

在每个时钟周期初始化为 0，

duration

是对信号进行积分的周期数。 然而，在我所有的测试平台中，

integral

从不假设除 0 之外的任何值。我不确定到底发生了什么？帮助解决故障排除将不胜感激。

完整代码在这里：

module VariableIntegrator  (
        input [15:0] x,
        input clk, reset,
        input [7:0] duration, interval,
        output reg [63:0] integral
    );

    reg [15:0] memory [31:0];
    reg [7:0] i;

    always @ (posedge clk) begin
        if (reset) begin

            integral    <= 64'd0;
            memory[0]   <= 16'd0;
            memory[1]   <= 16'd0;
            memory[2]   <= 16'd0;
            memory[3]   <= 16'd0;
            memory[4]   <= 16'd0;
            memory[5]   <= 16'd0;
            memory[6]   <= 16'd0;
            memory[7]   <= 16'd0;
            memory[8]   <= 16'd0;
            memory[9]   <= 16'd0;
            memory[10]  <= 16'd0;
            memory[11]  <= 16'd0;
            memory[12]  <= 16'd0;
            memory[13]  <= 16'd0;
            memory[14]  <= 16'd0;
            memory[15]  <= 16'd0;
            memory[16]  <= 16'd0;
            memory[17]  <= 16'd0;
            memory[18]  <= 16'd0;
            memory[19]  <= 16'd0;
            memory[20]  <= 16'd0;
            memory[21]  <= 16'd0;
            memory[22]  <= 16'd0;
            memory[23]  <= 16'd0;
            memory[24]  <= 16'd0;
            memory[25]  <= 16'd0;
            memory[26]  <= 16'd0;
            memory[27]  <= 16'd0;
            memory[28]  <= 16'd0;
            memory[29]  <= 16'd0;
            memory[30]  <= 16'd0;
            memory[31]  <= 16'd0;

        end

        else begin

            memory[0]   <= x;
            memory[1]   <= memory[0];
            memory[2]   <= memory[1];
            memory[3]   <= memory[2];
            memory[4]   <= memory[3];
            memory[5]   <= memory[4];
            memory[6]   <= memory[5];
            memory[7]   <= memory[6];
            memory[8]   <= memory[7];
            memory[9]   <= memory[8];
            memory[10]  <= memory[9];
            memory[11]  <= memory[10];
            memory[12]  <= memory[11];
            memory[13]  <= memory[12];
            memory[14]  <= memory[13];
            memory[15]  <= memory[14];
            memory[16]  <= memory[15];
            memory[17]  <= memory[16];
            memory[18]  <= memory[17];
            memory[19]  <= memory[18];
            memory[20]  <= memory[19];
            memory[21]  <= memory[20];
            memory[22]  <= memory[21];
            memory[23]  <= memory[22];
            memory[24]  <= memory[23];
            memory[25]  <= memory[24];
            memory[26]  <= memory[25];
            memory[27]  <= memory[26];
            memory[28]  <= memory[27];
            memory[29]  <= memory[28];
            memory[30]  <= memory[29];
            memory[31]  <= memory[30];

            for (i=0; i < duration; i = i+1) begin
                integral <= integral + memory[i];
            end
            integral <= integral * interval;
        end
    end
endmodule

Answer 1

在你的always块中，后面对“integral”的分配将覆盖for循环中的前一个分配。那么“积分”就不会从“内存”中更新了。

for (i=0; i < duration; i = i+1) begin
    integral <= integral + memory[i];
end
integral <= integral * interval

您可以将“积分”的组合部分移动到另一个始终块，如下所示：

reg [63:0] integral_next;
always @*
begin: blk1
    reg [7:0] i;
    integral_next = integral;  // Default
    for ( i=0; i<duration; i=i+1 ) begin
        integral_next = integral_next + memory[i];
    end
    integral_next = integral_next * interval;
end

然后将“积分”的赋值替换为：

integral <= integral_next;