移位寄存器在Verilog HDL中不工作

Question

我想在Verilog HDL中设计一个64位的Shift寄存器，但是当我用testbench测试代码时，所有的位都是0。我不知道我哪里做错了。下面是我的代码和测试台的结果。

module ShiftRegister (shift_out, clk, shift_in, rst); //module ports
 parameter n = 64; //Parameter n declared to store 64
 input rst;
 input [n-1:0] shift_in; //64-bit input shift_in
 input clk; //Input clock
 output [n-1:0] shift_out; //64-bit output shift_out
 reg [n-1:0] ff; //64-bit flipflop
  assign shift_out = ff [n-1:0]; //give the output of the 64th bit
  //The operation of verilog: 
   always @ (posedge clk or posedge rst) //Always at the rising edge of the clock
   begin
     if (rst) begin
     ff <= 0;
   end else begin
     ff <= ff << 1;  //Shift bits to the left by 1
     ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
   end
   end
 endmodule


 module ShiftRegister_tb; //Module shiftRegister_tb
  parameter n = 64; //Parameter n declared to store 64
  reg [n-1:0] shift_in; //64-bit register input shift_in
  reg clk, rst; //register clock
  wire [n-1:0] shift_out; //64-bit wire output shift_out
  ShiftRegister DUT(shift_out, clk, shift_in,rst); //Calling the module
   initial
   begin
     clk = 0; //clock = 0 initally
     rst = 1;
     shift_in = 64'd34645767785344; //Random decimal number to test the code 
     #100;
     rst = 0;
     #50_000 $finish;
   end   
  always #50 clk =~clk; //invert the clock input after 50ps
 endmodule //ShiftRegister testbench 

Answer 1

这里是我的代码和测试台... ff[0] <= shift_in;你正试图将一个64位的变量赋值给1位的变量。因为你使用的是偶数 (64'd34645767785344)为 shift_in 在您的测试平台中，它的LSB是 0. 因此，你不断插入0到 ff.

让你的 shift_in 输入1位，并改变你的测试台，使你每次给1位作为输入。