PLL电压缩放STM32

问题描述 投票:0回答:1

我正在使用STM32F767 Nucleo板,目前,我试图将PLL设置为系统时钟。尽管能够,但是由于CubeMX生成了一个示例,我真的不明白为什么必须这样做。设置为:

  • HSI = 16MHz
  • PLLM = 8
  • VCO_Input_Frequency = 16/8 = 2MHz
  • PLLN = 144
  • 频率= 144 * 2 = 288MHz
  • PLLP = 6
  • PLL_Output_Frequency = 288/6 = 48MHz

  • PPRE1 = 2
  • APB1_Frequency = 24MHz
  • APB1_Frequency_Timer = 2 * 24MHz = 48MHz

下面的代码行困扰着我:

//Sets the voltage scaling mode to 3, VOS = 0x1 = b1
PWR->CR1 |= PWR_CR1_VOS_0;
a = PWR->CR1;       //Small delay

注释此行时,周期为19.7ms,处于活动状态时,周期为20ms,这是预期的。很奇怪,这是CubeMX生成的代码的作用。它将电压缩放为1(低性能)。我不明白如何将电压比例设置为等于1才能使PLL正常工作。

下面是配置PLL的代码:

void sys_clock_init(void){
int a;

//Sets the wait states to 1
FLASH->ACR |= 0x01;
a = FLASH->ACR;         //Small delay

//Enables the power interface (for the power controller)
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
a = RCC->APB1ENR;       //Small delay

//Clears the bits for the voltage scaling
PWR->CR1 &= ~(PWR_CR1_VOS);

//Sets the voltage scaling mode to 3, VOS = 0x1 = b1
PWR->CR1 |= PWR_CR1_VOS_0;
a = PWR->CR1;       //Small delay

//Makes HSI the source of the PLL
RCC->PLLCFGR &= ~(0x400000);

//Clears the bits for the different factors
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLM);

//Sets the PLLM = 0x08 = b100
RCC->PLLCFGR |= (RCC_PLLCFGR_PLLM_3);

//Clears the PLLN bits
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN);

//Sets PLLN = 0x90 = b10010000
RCC->PLLCFGR |=(RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLN_4);

//Clears the PLLP bits
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLP);

//Sets the PLLP = 0x02 = b10
RCC->PLLCFGR |=(RCC_PLLCFGR_PLLP_1);.

//Clears the PPRE1 bits
RCC->CFGR &= ~(RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0);

//Set bit PPRE1 = 0x02 = b100
RCC->CFGR |= (RCC_CFGR_PPRE1_2);// | RCC_CFGR_PPRE1_0);

//Turns the PLL ON
RCC->CR |= RCC_CR_PLLON;

//Waits for the PLL to be ready
while(!((RCC->CR & RCC_CR_PLLRDY) == RCC_CR_PLLRDY));

//Clears the switch bits
RCC->CFGR &= ~(RCC_CFGR_SW);

//Set the PLL as the System Clock
RCC->CFGR |= (RCC_CFGR_SW_1);}

我还测试过注释将CubeMX代码上的VOS位置1的行,并且周期像我一样是19.75ms。

microcontroller stm32
1个回答
0
投票

这是我的代码,使用PLL和外部时钟将板子升至16Mhz。

static int clock_init ( void )
{
    unsigned int ra;

    //switch to external clock.
    ra=GET32(RCC_CR);
    ra|=1<<16;
    PUT32(RCC_CR,ra);
    while(1) if(GET32(RCC_CR)&(1<<17)) break;
    if(1)
    {
        ra=GET32(RCC_CFGR);
        ra&=~3;
        ra|=1;
        PUT32(RCC_CFGR,ra);
        while(1) if(((GET32(RCC_CFGR)>>2)&3)==1) break;
    }
    //HSE ready
    //PLLM aim for 2mhz so 8/4=2
    //PLLN input is 2, want >=100 and <=432 so between 50 and 216
    //PLLP  16Mhz*8 = 128, 16MHz*6 = 96, not enough
    //so PLLP is 8 VCO 128 so PLLN is 64
    //dont really care about PLLQ but have to have something so 8
    PUT32(RCC_PLLCFGR,0x20000000|(8<<24)|(1<<22)|(3<<16)|(64<<6)|(4<<0));
    ra=GET32(RCC_CR);
    ra|=1<<24;
    PUT32(RCC_CR,ra);
    while(1) if(GET32(RCC_CR)&(1<<25)) break;
    ra=GET32(RCC_CFGR);
    ra&=~3;
    ra|=2;
    PUT32(RCC_CFGR,ra);
    while(1) if(((GET32(RCC_CFGR)>>2)&3)==2) break;

    return(0);
}

PUT32 / GET32是执行str / ldr的抽象函数。我将尝试使用48 HSE或48Mhz HSI,然后发布我发现的内容。

static int clock_init ( void )
{
    unsigned int ra;
    //PLLM aim for 2mhx so 16/8 = 2;
    //PLLN input is 2, want >=100 and <=432 so between 50 and 216
    //PLLN = 144, VCO 288
    //PLLP = 6, output 288/6 = 48MHz
    //dont really care about PLLQ but have to have something so 6
    PUT32(RCC_PLLCFGR,0x20000000|(6<<24)|(0<<22)|(2<<16)|(144<<6)|(8<<0));
    ra=GET32(RCC_CR);
    ra|=1<<24;
    PUT32(RCC_CR,ra);
    while(1) if(GET32(RCC_CR)&(1<<25)) break;
    ra=GET32(RCC_CFGR);
    ra&=~3;
    ra|=2;
    PUT32(RCC_CFGR,ra);
    while(1) if(((GET32(RCC_CFGR)>>2)&3)==2) break;

    return(0);
}

乌尔特作品,但这并不多说。

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