Verilog 代码在模拟中为信号获取 X

问题描述 投票：0回答：1

我是verilog新手，我有两个Verilog模块和一个作为topmodule的main.v模块，我想用vivado xilinx模拟它。这是我的主要模块。当我尝试模拟它时，我得到信号的 X 值。而且不知道是不是口岸申报的问题？

module main(
 
    clk2,
    inputsample0,
    inputsample1,
    outvec,
    rst
    );
    
    
parameter  N = 10;
parameter L =10;
integer M;
integer d;
reg [N-1 : 0] vector_class [9 : 0];
input  clk2;
input rst;
output reg outvec;
input inputsample0  ;
input inputsample1 ;
reg [N-1 : 0] feat_value [19:0];
reg [N-1 : 0] ch [19:0];
reg [N-1 : 0] feat [3:0];
reg [N-1 : 0] t1;
reg [N-1 : 0] t2;
reg [N-1 : 0] t3;
reg [N-1 : 0] distance [9:0];
reg [9:0] sum_dis;
wire  [N-1 : 0] inter_port;
reg [4:0] minVal;

assign clk2 = 1;


parameter threshold_value = 50;
reg [31:0] rng_seed;
integer rand_normal;
integer i;
integer a;
integer c;
integer rel_dist;
integer j;
integer f;
integer min_dist;    
assign inputsample0 = 4'b0101; // Assigning decimal value 5 to inputsample
// Wait for 10 time units
assign inputsample1 = 4'b0110; // Assigning decimal value 6 to inputsample



Asocciate_mem2 asocciate_mem2_inst (
    .outvec(inter_port),
    .clk(clk2),
    .rst(rst)
);


hamming hamming_inst (
    .input_vector(inter_port), // Connect the wire to the textVector input
    .clk(clk2)
);   
endmodule

这是我的另外两个模块：

module Asocciate_mem2(
    outvec,
    inputsample,
    clk,
    rst
    );
    
parameter  N = 10;
parameter L =10;
integer M;
integer d;

input clk;
input rst;
input [3 : 0]inputsample  ;
reg [N-1 : 0] feat_value [19:0];
reg [N-1 : 0] ch [19:0];
reg [N-1 : 0] feat [1:0];
reg [N-1 : 0] t1;
reg [N-1 : 0] t2;
reg [N-1 : 0] t3;
reg [N-1 : 0] distance [9:0];
reg [9:0] sum_dis;

reg [4:0] minVal;
reg [N-1 : 0] textVector;
output [N-1 : 0] outvec;


parameter threshold_value = 50;
reg [31:0] rng_seed;
integer rand_normal;
integer i;
integer a;
integer c;
integer rel_dist;
integer j;
integer f;

integer min_dist;
    // Random number generator for Verilog 'normal' distribution (mean=0, std_dev=1)
    task rand_n;
        begin
        // Initialize random number
            
        // Generate a single random bit using XOR shift algorithm
            for (i = 0; i < 1; i = i + 1) begin
            // XOR shift algorithm for generating random numbers
                rng_seed = rng_seed ^ (rng_seed << 13);
                rng_seed = rng_seed ^ (rng_seed >> 17);
                rng_seed = rng_seed ^ (rng_seed << 5);
            // Assign a value of 1 if the random number exceeds a threshold
                if (rng_seed > threshold_value) begin
                    rand_normal <= 1;
                end
                else begin
                    rand_normal <= 0;
                end
            end
        end
    endtask


   



always @(posedge clk) begin

        feat_value[ 0] <=1000'b1101001011;
        feat_value[ 1] <=1000'b1010010101;
        feat_value[ 2] <=1000'b1101001010;
        feat_value[ 3] <=1000'b1101001010;
        feat_value[ 4] <=1000'b1101001010;
        feat_value[ 5] <=1000'b1101001011;
        feat_value[ 6] <=1000'b1010010101;
        feat_value[ 7] <=1000'b1101001010;
        feat_value[ 8] <=1000'b1101001010;
        feat_value[ 9] <=1000'b1101001010;
        feat_value[ 10] <=1000'b1101001011;
        feat_value[ 11] <=1000'b1010010101;
        feat_value[ 12] <=1000'b1101001010;
        feat_value[ 13] <=1000'b1101001010;
        feat_value[ 14] <=1000'b1101001010;
        feat_value[ 15] <=1000'b1101001011;
        feat_value[ 16] <=1000'b1010010101;
        feat_value[ 17] <=1000'b1101001010;
        feat_value[ 18] <=1000'b1101001010;
        feat_value[ 19] <=1000'b1101001010;                   
        
        
end
always @(posedge clk) begin

         feat[ 0]<=1000'b1101001010;

         feat[ 1]<=1000'b1101001010;
         //feat[ 2]<=1000'b1101001010;
 
         //feat[ 3]<=1000'b1101001010;
 
        
end
always @(posedge clk) begin

      for (c =0; c<2; c = c+1)begin
           t3 <= 0;
           t2 <=0;
           t1 <= 0;   
           for (f=0; f<2; f = f+1)begin
             
        
              t1 <= feat_value[inputsample[f]];
              t2 <= feat[f] ^ t1;
              t3 <= t3+t2;
           end
           
           textVector <= textVector + t3;
          
            
         
      end
end

assign outvec = textVector;


endmodule

module hamming(
  
    clk,
    
     input_vector
    );
    
parameter  N = 10;
input [N-1 : 0]  input_vector;    
reg [N-1 : 0] vector_class [9 : 0];    

parameter L =10;
reg [9:0] sum_dis;
input clk;
 reg [4:0] minVal;
integer rel_dist;
integer j;
reg [N-1 : 0] distance [9:0];
integer M;
integer d;   
integer min_dist;    


always@(posedge clk) begin

        vector_class[ 0] <=1000'b1101001010;
        vector_class[ 1] <=1000'b1101001010;
        vector_class[ 2] <=1000'b1101001010;
        vector_class[ 3] <=1000'b1101001010;
        vector_class[ 4] <=1000'b1101001010;
        vector_class[ 5] <=1000'b1101001010;
        vector_class[ 6] <=1000'b1101001010;
        vector_class[ 7] <=1000'b1101001010;
        vector_class[ 8] <=1000'b1101001010;
        vector_class[ 9] <=1000'b1101001010;    
end 

always @(posedge clk) begin
      for (M =0;M <N; M=M+1)begin
            rel_dist <= 0; 
            for (d =0; d< 10; d=d+1)begin
                distance[M][d] <= vector_class[d] ^  input_vector;
                if (distance[M][d] == 1'b1) begin
                    rel_dist <= rel_dist + 1;
                end
                sum_dis[d] <= rel_dist;
            end
        end
        min_dist=sum_dis[0];
        minVal = 0;
        for ( j = 1; j < 10; j = j + 1) begin
            if (sum_dis[j] < min_dist) begin
                min_dist = sum_dis[j];
                minVal = j;
            end
        end

       
       
end
   
    
endmodule
verilog simulation xilinx vivado
1个回答
0
投票

非阻塞赋值 (

<=
) 立即计算表达式，但在 Verilog 调度程序中推迟对 NBA 区域的赋值。因此，在评估表达式时，使用 
t1
、
t2
、
t3
等使用先前的值。在大多数情况下，初始值为 
x
。

假设

Asocciate_mem2
中的功能准确，建议将逻辑分为组合和顺序组件

// combinational logic, use auto-sensitivity list (@*) and assign with blocking assignments (=)
always @* begin
  next_textVector = textVector; // init/default value
  for (c =0; c<2; c = c+1)begin
    t3 = 0;
    t2 = 0;
    t1 = 0;   
    for (f=0; f<2; f = f+1)begin
      t1 = feat_value[inputsample[f]];
      t2 = feat[f] ^ t1;
      t3 = t3+t2;
    end
    next_textVector = next_textVector + t3;
  end
end

// sequential logic, use clock edge event and assign with non-blocking assignments (<=)
always @(posedge clk) begin
  if (rst) begin // assuming active-high synchronous reset
    textVector <= 0;
  end
  else begin
    textVector <= next_textVector; // synchronize value
  end
end


hamming
模块也有类似的问题。它还缺乏输出。

clk2
中的
main
是一个输入并被赋值。这可能会造成驱动程序冲突，导致
x
。不要分配作为当前示波器输入的信号。此外，时钟通常需要切换。

除非您特别要求以 Verilog-95 风格进行编码，否则建议更改为使用 Verilog-2001 中引入的 ANSI 风格模块头。它更简洁，更容易阅读，并且更少的拼写错误。示例：

module Asocciate_mem2 #(
   parameter  N = 10,
   parameter  L = 10,
   parameter threshold_value = 50
  )(
    output [N-1 : 0]  outvec,
    input  [  3 : 0]  inputsample,
    input             clk,
    input             rst
  );

  reg [N-1 : 0] feat_value [19:0];
  reg [N-1 : 0] ch [19:0];
  reg [N-1 : 0] feat [1:0];
  // ...
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