精化任务“$dumpvars”需要 SystemVerilog
是我执行时在终端中显示的错误
iverilog -o test_tb.vvp test_tb.v
类似$dumpvars
代码是
//设计
module test (a,b);
input a;
output b;
assign b=a;
endmodule
//测试平台
`timescale 1ns/1ns
`include "test.v"
module test_tb ();
reg a;
wire b;
test uut(a,b);
$dumpfile("test_tb.vcd");
$dumpvars(0,test_tb);
initial begin
a=0;
#20;
a=1;
#20;
a=0;
#20;
$display("test complete");
end
endmodule
系统任务调用需要像这样在初始块中:
initial begin
$dumpfile("test_tb.vcd");
$dumpvars(0,test_tb);
end