我正在使用C语言在STM32F103C6上使用BAREMETAL对UART进行编程。但是,当我在Proteus软件中对其进行模拟时,它不起作用!我使用 HAL 制作了另一个程序,完成了这项工作,但没有使用 BAREMETAL 中的代码。谁能帮我找出我的错误吗?
#include "stm32f103x6.h"
#define USART2EN (1U<<17)
#define GPIOAEN (1U<<2)
#define CR1_UE (1U<<13)
#define CR1_M (1U<<12)
#define CR1_TE (1U<<3)
#define CR1_RE (1U<<2)
#define SR_TXE (1U<<7)
#define SR_RXNE (1U<<5)
#define SR_TC (1U<<6)
#define BAUDRATE 115200
#define APB1_FREQ 8000000
/*Função que configura o clock*/
void SysClockConfig(void)
{
/***********>>>> PASSO A PASSO <<<<***********
* 1. ENABLE HSI and wait to become ready internal 8 MHz RC Oscillator
* 2. Set the POWER ENABLE CLOCK
* 3. Configure the PRESCALERS MCLK, PCLK1, PCLK2 (peripheral clocks)
**********************************************/
//1. ENABLE HSE and wait for the MSE to become ready (external crystal)
RCC->CR |= RCC_CR_HSION; // habilita o clock externo
while (!(RCC->CR & RCC_CR_HSIRDY)){} // quer dizer que o oscilador estar pronto
//2. Set the POWER ENABLE CLOCK
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
//Desabilita o PLL primeiro
RCC->CR &=~ (1U<<24);
while (!(RCC->CR & (1U<<25))){} // aguarda ate o PLL ser desligado
//Configura o PLL para HSI/2 * 2 = 8Mhz (sendo o HSI = 8MHz)
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); // primeiro zera os bits
// Deixa os bits 18 a 21 PLLMUL = 0000 = PLL input clock x 2
RCC->CFGR &=~ (1U<<18);
RCC->CFGR &=~ (1U<<19);
RCC->CFGR &=~ (1U<<20);
RCC->CFGR &=~ (1U<<21);
// Deixa o bit 16 PLLSRC = 0 = HSI oscillator clock / 2 selected as PLL input clock
RCC->CFGR &=~ (1U<<16);
//Habilita o PLL
RCC->CR |= (1U<<24);
while (RCC->CR & (1U<<25)){} // aguarda ate o PLL estar pronto
//3. Configurar os PRESCALERS AHB, APB1 e APB2 (peripheral clocks)
//AHB PR
RCC->CFGR |= RCC_CFGR_HPRE_DIV1; // divide por 1
//APB1 PR
RCC->CFGR |= RCC_CFGR_PPRE1_DIV1;// divide por 1
//APB2 PR
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;// divide por 1
// Seleciona o clock do sistema para PLL
RCC->CFGR &=~ RCC_CFGR_SW;
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); // Espera ate que o PLL seja selecionado como clock
}
接下来我进行了 UART 设置
void uart2_tx_init(void)
{
/*** CONFIGURA O GPIOA QUE É ONDE ESTA CONECTADO O TX DO UART2 ***/
/* 1- Habilitar o sinal de clock ao GPIO A*/
RCC->APB2ENR |= GPIOAEN;
/*Configurar o PA2 (TX) e PA3 (RX)*/
//PA2
GPIOA->CRL &=~(GPIO_CRL_CNF2 | GPIO_CRL_MODE2 | GPIO_CRL_CNF3 | GPIO_CRL_MODE3);
GPIOA->CRL &=~(1U<<8);//seta bit 8 para 0
GPIOA->CRL |= (1U<<9);//seta bit 9 para 1
GPIOA->CRL &=~ (1U<<10);//seta bit 10 para 0
GPIOA->CRL |= (1U<<11);//seta bit 11 para 1
//PA3
GPIOA->CRL &=~(1U<<12);//seta bit 12 para 0
GPIOA->CRL |= (1U<<13);//seta bit 13 para 1
GPIOA->CRL &=~ (1U<<14);//seta bit 14 para 0
GPIOA->CRL |= (1U<<15);//seta bit 15 para 1
/*** CONFIGURA O PERIFERICO UART ***/
/* 1- Habilitar o sinal de clock ao periferico UART2*/
RCC->APB1ENR |= USART2EN;
/*Habilitar o USART no registrador de controle*/
USART2->CR1 |= CR1_UE;
/*Seleciona para 1 Start bit, 8 Data bits, n Stop bit */
USART2->CR1 &=~ CR1_M;
/*Numero de Stop bits em 1*/
USART2->CR2 &=~ (1U<<12);
USART2->CR2 &=~ (1U<<13);
/*Configura o Baud Rate com fclk de 8Mhz e bd 1500*/
USART2->BRR = (5U<<0) | (4U<<4);//(unsigned)(APB1_FREQ/BAUDRATE);
/*Habilita a transferencia (Tx) -> to send an idle frame as first transmission.*/
USART2->CR1 |= CR1_TE;
/*Habilida o recebimento*/
USART2->CR1 |= CR1_RE;
}
在里面我做了可以发送和接收的功能
void UART2_SendChar(int ch)
{
while (!(USART2->SR & SR_TXE)){}
USART2->DR = (ch & 0xFF);
}
char UART2_ReceiveChar(void)
{
while (!(USART2->SR & SR_RXNE)); // Espera até receber um caractere
return USART2->DR; // Retorna o caractere recebido
}
int main (void)
{
SysClockConfig();
uart2_tx_init();
while(1)
{
UART2_SendChar('m');
}
}
可以使用STM32CubeIDE调试SMT32F103C6(BluePill)吗?我的 MCU 是假的,我不确定是否可以直接在 STM32CubeIDE 上进行调试。如果有人知道怎么做,可以给我解释一下吗?