BeagleBone AI - 如何设置CAN总线？

问题描述 投票：0回答：1

在网上找不到任何关于在小猎犬骨牌AI上设置CAN总线的资源，好不容易上手了，但是zmatt上的 http:/beagleboard.orgchat 基本上为我做了所有的事情来帮助我启动和运行，所以，#1请大家感谢zmatt，#2我想在这里分享我的发现，所以其他人不需要经历所有的痛苦，我经历了所有的痛苦来启动和运行。

基本的问题是，BeagleBone AI不能开箱使用CAN总线。主要原因是默认情况下，pinxmux配置不正确。

解决问题的步骤。

下载一个适合你设备的Linux内核版本。我用的是测试版。

 https://elinux.org/Beagleboard:Latest-images-testing
 am57xx-debian-10.3-console-armhf-2020-04-06-1gb.img.xz

注：这是一个 "控制台 "版本，意味着你必须自己安装所有的应用程序。基本上，每次你尝试一个命令而失败时，google Linux install（无论什么命令失败）。否则，你可以尝试一个基本的Beagle Bone AI发行版，它将默认包含应用程序。

设置你的网络配置，这样你就可以在BBAI中下载任何你需要的东西。在我的情况下，我将BBAI连接到WIFI，所以通过连接它。 https: /fis. gatech. edu how toconfigure -bbww -wifi.

下载设备树源码。

Note!!!! Which ever version of Linux you are using, you MUST make sure the source code branch you are using matches your Linux version!!!!
   cd ~
   mkdir DeviceTree
   #The following command will create a folder BeagleBoard-DeviceTrees in the current directory with the device tree.
   git clone https://github.com/beagleboard/BeagleBoard-DeviceTrees.git
   #For instance, if you are using version 4.14 of the TI linux, set the GIT branch to:
   #Note 2: make sure it is the TI version (-ti)
   git checkout v4.14.x-ti

好了，这里是秘诀。使用下面zmatt创建的DTS。将文件保存在~DeviceTreeBeagleBoard-DeviceTreessrcarmbbai-custom.dts中。

文件内容。

#include "am5729-beagleboneai.dts"

&{/chosen} {
    base_dtb = "bbai-custom.dts";   // <-- name of this file goes here
};

#define P9_24   ( 0x3400 + 4 * 163 )
#define P9_26a  ( 0x3400 + 4 * 162 )
#define P9_26b  ( 0x3400 + 4 *  81 )

&dra7_pmx_core {
    can1_pins_active: can1-active {
        pinctrl-single,pins = <
            DRA7XX_CORE_IOPAD( P9_24,  PIN_INPUT_PULLUP  | MUX_MODE2  ) // rx
            DRA7XX_CORE_IOPAD( P9_26a, PIN_OUTPUT_PULLUP | MUX_MODE2  ) // tx
        >;
    };

    can1_pins_sleep: can1-sleep {
        pinctrl-single,pins = <
            DRA7XX_CORE_IOPAD( P9_24,  PIN_OUTPUT_PULLUP | MUX_MODE15 ) // rx (disabled)
            DRA7XX_CORE_IOPAD( P9_26a, PIN_OUTPUT_PULLUP | MUX_MODE15 ) // tx (disabled)
        >;
    };

    can1_pins_init: can1-init {
        pinctrl-single,pins = <
            DRA7XX_CORE_IOPAD( P9_26b, PIN_OUTPUT        | MUX_MODE15 ) // disable unused shared pin
        >;
    };
};

&dcan2 {  // <---- not a typo
    status = "ok";
    pinctrl-names = "init", "default", "sleep", "active";
    pinctrl-0 = <&can1_pins_sleep>, <&can1_pins_init>;
    pinctrl-1 = <&can1_pins_sleep>;
    pinctrl-2 = <&can1_pins_sleep>;
    pinctrl-3 = <&can1_pins_active>;
};

// Here's the obnoxious part: since u-boot doesn't have same pin defaults yet, all pins not  
// explicitly setup above should be overridden here.  This will eventually no longer be needed.  
&cape_pins_default {
    pinctrl-single,pins = <
        DRA7XX_CORE_IOPAD(0x379C, MUX_MODE14) /* AB8: P8.3: mmc3_dat6.off */
        DRA7XX_CORE_IOPAD(0x37A0, MUX_MODE14) /* AB5: P8.4: mmc3_dat7.off */
        DRA7XX_CORE_IOPAD(0x378C, MUX_MODE14) /* AC9: P8.5: mmc3_dat2.off */
        DRA7XX_CORE_IOPAD(0x3790, MUX_MODE14) /* AC3: P8.6: mmc3_dat3.off */
        DRA7XX_CORE_IOPAD(0x36EC, MUX_MODE14) /* G14: P8.7: mcasp1_axr14.off */
        DRA7XX_CORE_IOPAD(0x36F0, MUX_MODE14) /* F14: P8.8: mcasp1_axr15.off */
        DRA7XX_CORE_IOPAD(0x3698, MUX_MODE14) /* E17: P8.9: xref_clk1.off */
        DRA7XX_CORE_IOPAD(0x36E8, MUX_MODE14) /* A13: P8.10: mcasp1_axr13.off */
        DRA7XX_CORE_IOPAD(0x3510, MUX_MODE14) /* AH4: P8.11: vin1a_d7.off */
        DRA7XX_CORE_IOPAD(0x350C, MUX_MODE14) /* AG6: P8.12: vin1a_d6.off */
        DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE12) /* D3: P8.13: vin2a_d10.off */
        DRA7XX_CORE_IOPAD(0x3598, MUX_MODE14) /* D5: P8.14: vin2a_d12.off */
        DRA7XX_CORE_IOPAD(0x3570, MUX_MODE14) /* D1: P8.15a: vin2a_d2.off */
        DRA7XX_CORE_IOPAD(0x35B4, MUX_MODE13) /* A3: P8.15b: vin2a_d19.off */
        DRA7XX_CORE_IOPAD(0x35BC, MUX_MODE13) /* B4: P8.16: vin2a_d21.off */
        DRA7XX_CORE_IOPAD(0x3624, MUX_MODE14) /* A7: P8.17: vout1_d18.off */
        DRA7XX_CORE_IOPAD(0x3588, PIN_INPUT | MUX_MODE12) /* F5: P8.18: vin2a_d8.off */
        DRA7XX_CORE_IOPAD(0x358C, PIN_INPUT | MUX_MODE12) /* E6: P8.19: vin2a_d9.off */
        DRA7XX_CORE_IOPAD(0x3780, MUX_MODE14) /* AC4: P8.20: mmc3_cmd.off */
        DRA7XX_CORE_IOPAD(0x377C, MUX_MODE14) /* AD4: P8.21: mmc3_clk.off */
        DRA7XX_CORE_IOPAD(0x3798, MUX_MODE14) /* AD6: P8.22: mmc3_dat5.off */
        DRA7XX_CORE_IOPAD(0x3794, MUX_MODE14) /* AC8: P8.23: mmc3_dat4.off */
        DRA7XX_CORE_IOPAD(0x3788, MUX_MODE14) /* AC6: P8.24: mmc3_dat1.off */
        DRA7XX_CORE_IOPAD(0x3784, MUX_MODE14) /* AC7: P8.25: mmc3_dat0.off */
        DRA7XX_CORE_IOPAD(0x35B8, MUX_MODE13) /* B3: P8.26: vin2a_d20.off */
        DRA7XX_CORE_IOPAD(0x35D8, MUX_MODE14) /* E11: P8.27a: vout1_vsync.off */
        DRA7XX_CORE_IOPAD(0x3628, MUX_MODE14) /* A8: P8.27b: vout1_d19.off */
        DRA7XX_CORE_IOPAD(0x35C8, MUX_MODE14) /* D11: P8.28a: vout1_clk.off */
        DRA7XX_CORE_IOPAD(0x362C, MUX_MODE14) /* C9: P8.28b: vout1_d20.off */
        DRA7XX_CORE_IOPAD(0x35D4, MUX_MODE14) /* C11: P8.29a: vout1_hsync.off */
        DRA7XX_CORE_IOPAD(0x3630, MUX_MODE14) /* A9: P8.29b: vout1_d21.off */
        DRA7XX_CORE_IOPAD(0x35CC, MUX_MODE14) /* B10: P8.30a: vout1_de.off */
        DRA7XX_CORE_IOPAD(0x3634, MUX_MODE14) /* B9: P8.30b: vout1_d22.off */
        DRA7XX_CORE_IOPAD(0x3614, MUX_MODE14) /* C8: P8.31a: vout1_d14.off */
        DRA7XX_CORE_IOPAD(0x373C, MUX_MODE14) /* G16: P8.31b: mcasp4_axr0.off */
        DRA7XX_CORE_IOPAD(0x3618, MUX_MODE14) /* C7: P8.32a: vout1_d15.off */
        DRA7XX_CORE_IOPAD(0x3740, MUX_MODE14) /* D17: P8.32b: mcasp4_axr1.off */
        DRA7XX_CORE_IOPAD(0x3610, MUX_MODE14) /* C6: P8.33a: vout1_d13.off */
        DRA7XX_CORE_IOPAD(0x34E8, MUX_MODE14) /* AF9: P8.33b: vin1a_fld0.off */
        DRA7XX_CORE_IOPAD(0x3608, MUX_MODE14) /* D8: P8.34a: vout1_d11.off */
        DRA7XX_CORE_IOPAD(0x3564, MUX_MODE14) /* G6: P8.34b: vin2a_vsync0.off */
        DRA7XX_CORE_IOPAD(0x360C, MUX_MODE14) /* A5: P8.35a: vout1_d12.off */
        DRA7XX_CORE_IOPAD(0x34E4, MUX_MODE14) /* AD9: P8.35b: vin1a_de0.off */
        DRA7XX_CORE_IOPAD(0x3604, MUX_MODE14) /* D7: P8.36a: vout1_d10.off */
        DRA7XX_CORE_IOPAD(0x3568, MUX_MODE14) /* F2: P8.36b: vin2a_d0.off */
        DRA7XX_CORE_IOPAD(0x35FC, MUX_MODE14) /* E8: P8.37a: vout1_d8.off */
        DRA7XX_CORE_IOPAD(0x3738, MUX_MODE14) /* A21: P8.37b: mcasp4_fsx.off */
        DRA7XX_CORE_IOPAD(0x3600, MUX_MODE14) /* D9: P8.38a: vout1_d9.off */
        DRA7XX_CORE_IOPAD(0x3734, MUX_MODE14) /* C18: P8.38b: mcasp4_aclkx.off */
        DRA7XX_CORE_IOPAD(0x35F4, MUX_MODE14) /* F8: P8.39: vout1_d6.off */
        DRA7XX_CORE_IOPAD(0x35F8, MUX_MODE14) /* E7: P8.40: vout1_d7.off */
        DRA7XX_CORE_IOPAD(0x35EC, MUX_MODE14) /* E9: P8.41: vout1_d4.off */
        DRA7XX_CORE_IOPAD(0x35F0, MUX_MODE14) /* F9: P8.42: vout1_d5.off */
        DRA7XX_CORE_IOPAD(0x35E4, MUX_MODE14) /* F10: P8.43: vout1_d2.off */
        DRA7XX_CORE_IOPAD(0x35E8, MUX_MODE14) /* G11: P8.44: vout1_d3.off */
        DRA7XX_CORE_IOPAD(0x35DC, MUX_MODE14) /* F11: P8.45a: vout1_d0.off */
        DRA7XX_CORE_IOPAD(0x361C, MUX_MODE14) /* B7: P8.45b: vout1_d16.off */
        DRA7XX_CORE_IOPAD(0x35E0, MUX_MODE14) /* G10: P8.46a: vout1_d1.off */
        DRA7XX_CORE_IOPAD(0x3638, MUX_MODE14) /* A10: P8.46b: vout1_d23.off */
        DRA7XX_CORE_IOPAD(0x372C, MUX_MODE14) /* B19: P9.11a: mcasp3_axr0.off */
        DRA7XX_CORE_IOPAD(0x3620, MUX_MODE14) /* B8: P9.11b: vout1_d17.off */
        DRA7XX_CORE_IOPAD(0x36AC, MUX_MODE14) /* B14: P9.12: mcasp1_aclkr.off */
        DRA7XX_CORE_IOPAD(0x3730, MUX_MODE14) /* C17: P9.13: mcasp3_axr1.off */
        DRA7XX_CORE_IOPAD(0x35AC, MUX_MODE10) /* D6: P9.14: vin2a_d17.off */
        DRA7XX_CORE_IOPAD(0x3514, MUX_MODE14) /* AG4: P9.15: vin1a_d8.off */
        DRA7XX_CORE_IOPAD(0x35B0, MUX_MODE13) /* C5: P9.16: vin2a_d18.off */
        DRA7XX_CORE_IOPAD(0x37CC, MUX_MODE14) /* B24: P9.17a: spi2_cs0.off */
        DRA7XX_CORE_IOPAD(0x36B8, MUX_MODE14) /* F12: P9.17b: mcasp1_axr1.off */
        DRA7XX_CORE_IOPAD(0x37C8, MUX_MODE14) /* G17: P9.18a: spi2_d0.off */
        DRA7XX_CORE_IOPAD(0x36B4, MUX_MODE14) /* G12: P9.18b: mcasp1_axr0.off */
        DRA7XX_CORE_IOPAD(0x3440, PIN_INPUT_PULLUP | MUX_MODE7) /* R6: P9.19a: gpmc_a0.i2c4_scl */
        DRA7XX_CORE_IOPAD(0x357C, PIN_INPUT_PULLUP | MUX_MODE12 ) /* F4: P9.19b: vin2a_d5.pr1_pru1_gpi2 */
        DRA7XX_CORE_IOPAD(0x3444, PIN_INPUT_PULLUP | MUX_MODE7) /* T9: P9.20a: gpmc_a1.i2c4_sda */
        DRA7XX_CORE_IOPAD(0x3578, PIN_INPUT_PULLUP | MUX_MODE12) /* D2: P9.20b: vin2a_d4.pr1_pru1_gpi1 */
        DRA7XX_CORE_IOPAD(0x34F0, MUX_MODE14) /* AF8: P9.21a: vin1a_vsync0.off */
        DRA7XX_CORE_IOPAD(0x37C4, MUX_MODE14) /* B22: P9.21b: spi2_d1.off */
        DRA7XX_CORE_IOPAD(0x369C, MUX_MODE14) /* B26: P9.22a: xref_clk2.off */
        DRA7XX_CORE_IOPAD(0x37C0, MUX_MODE14) /* A26: P9.22b: spi2_sclk.off */
        DRA7XX_CORE_IOPAD(0x37B4, MUX_MODE14) /* A22: P9.23: spi1_cs1.off */
    //  DRA7XX_CORE_IOPAD(0x368C, MUX_MODE14) /* F20: P9.24: gpio6_15.off */
        DRA7XX_CORE_IOPAD(0x3694, MUX_MODE14) /* D18: P9.25: xref_clk0.off */
    //  DRA7XX_CORE_IOPAD(0x3688, MUX_MODE14) /* E21: P9.26a: gpio6_14.off */
    //  DRA7XX_CORE_IOPAD(0x3544, MUX_MODE14) /* AE2: P9.26b: vin1a_d20.off */
        DRA7XX_CORE_IOPAD(0x35A0, MUX_MODE14) /* C3: P9.27a: vin2a_d14.off */
        DRA7XX_CORE_IOPAD(0x36B0, MUX_MODE14) /* J14: P9.27b: mcasp1_fsr.off */
        DRA7XX_CORE_IOPAD(0x36E0, MUX_MODE14) /* A12: P9.28: mcasp1_axr11.off */
        DRA7XX_CORE_IOPAD(0x36D8, MUX_MODE14) /* A11: P9.29a: mcasp1_axr9.off */
        DRA7XX_CORE_IOPAD(0x36A8, MUX_MODE14) /* D14: P9.29b: mcasp1_fsx.off */
        DRA7XX_CORE_IOPAD(0x36DC, MUX_MODE14) /* B13: P9.30: mcasp1_axr10.off */
        DRA7XX_CORE_IOPAD(0x36D4, MUX_MODE14) /* B12: P9.31a: mcasp1_axr8.off */
        DRA7XX_CORE_IOPAD(0x36A4, MUX_MODE14) /* C14: P9.31b: mcasp1_aclkx.off */
        DRA7XX_CORE_IOPAD(0x36A0, MUX_MODE14) /* C23: P9.41a: xref_clk3.off */
        DRA7XX_CORE_IOPAD(0x3580, MUX_MODE14) /* C1: P9.41b: vin2a_d6.off */
        DRA7XX_CORE_IOPAD(0x36E4, MUX_MODE14) /* E14: P9.42a: mcasp1_axr12.off */
        DRA7XX_CORE_IOPAD(0x359C, MUX_MODE14) /* C2: P9.42b: vin2a_d13.off */
    >;
};

保存好DTS文本文件后，我们需要对其进行编译。GIT仓库允许我们轻松编译这个文件。

编译的方法是

  cd ~/DeviceTree/BeagleBoard-DeviceTrees

  #This should create a bbai-custom.dtb file
  make src/arm/bbai-custom.dtb

  #Verify that the file ~/DeviceTree/BeagleBoard-DeviceTrees/src/arm/bbai-custom.dtb after compiling.

将输出的二进制文件

  #Copy the output binary to the /boot directory so when we boot we can detect and use it.
  sudo cp src/arm/bbai-custom.dtb /boot/dtbs/bbai-custom.dtb

修改U-Boot启动设置文件。

  #Use whatever text editor you like to modify the following file
  sudo nano /boot/uEnv.txt

  Add the following to the file
  dtb=bbai-custom.dtb

  Save the file
  Reboot the machine

输入以下内容测试其是否有效

  #Type the following command in and can0 should be in the list
  ip link

最后警告! 我试着写下我所做的一切，以得到这个设置，但我不是100％的肯定，所有上述步骤是明确正确的。如果我做了一些复制粘贴，路径错误，或其他，请阅读字里行间。

希望这些都能帮到你。

linux linux-kernel u-boot can-bus
1个回答
0
投票

对于它的价值，几个月前我问过这个问题（后来我自己在BB邮件列表上回答了它）。https:/groups.google.comdmsgbeagleboard-0BqofMNKVwFpOSb4rzAAAJ。

我基本上和你做的一样，但是我的.dts文件比较短。我没有重新指定所有其他的引脚，它的工作就像这样。

#include "am5729-beagleboneai.dts"

/ {
    chosen {
        base_dtb = "am5729-beagleboneai-kitepower.dts";
        base_dtb_timestamp = __TIMESTAMP__;
    };
};

// The second name (pinmux_dcan2_pins) seems not used
&dra7_pmx_core {
    dcan2_pins: pinmux_dcan2_pins {
        pinctrl-single,pins = <
            /* P9_24: uart1_txd.d_can2_rx */
            DRA7XX_CORE_IOPAD(0x368C, PIN_INPUT_PULLUP | MUX_MODE2)
            /* P9_26: uart1_rxd.d_can2_tx */
            DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT_PULLUP | MUX_MODE2)
        >;
    };
};

// Initially defined in dra7 (which is included through multiple layers) as disabled
&dcan2 {
    pinctrl-names = "default"; // Not sure what this is used for
    pinctrl-0 = <&dcan2_pins>;
    status = "okay";
};
最新问题
© www.soinside.com 2019 - 2024. All rights reserved.