使用 VHDL 的 BASYS 3 板上的时钟分频器问题

Question

我正在尝试使用 VHDL 为 BASYS 3 板设置分频器。它在 Vivado 中模拟得很好，但我似乎无法让程序在实际硬件上运行。当我在硬件上运行它时，LED 微弱地亮起（我假设它以 50% 的占空比快速循环打开和关闭），但计时不起作用。 LED 应该以 50% 的占空比和 0.5 秒的周期闪烁。

仅供参考，我对一般的硬件设计语言和特别是 VHDL 都是新手。

约束

# Clock signal
set_property PACKAGE_PIN W5 [get_ports CLK100MHZ]                           
    set_property IOSTANDARD LVCMOS33 [get_ports CLK100MHZ]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK100MHZ]

--Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]


--LEDs
set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
set_property PACKAGE_PIN V13 [get_ports {LED[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}]
set_property PACKAGE_PIN V3 [get_ports {LED[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}]
set_property PACKAGE_PIN W3 [get_ports {LED[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}]
set_property PACKAGE_PIN U3 [get_ports {LED[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}]
set_property PACKAGE_PIN P3 [get_ports {LED[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}]
set_property PACKAGE_PIN N3 [get_ports {LED[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}]
set_property PACKAGE_PIN P1 [get_ports {LED[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}]
set_property PACKAGE_PIN L1 [get_ports {LED[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

VHDL 时钟分频器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--Declaration
entity HW2_3 is
    port(
            clk         :   in std_logic;               --Counter clock input
            clk_out     :   out std_logic := '0');      --Count flag output, true over half period
end HW2_3;

--implementation
architecture Behavioral of HW2_3 is
begin
    process(clk)
    
    variable count        : integer := 0;       --internal count variable   
    variable out_flag     : std_logic := '0';   --flag used to turn on/off clk_out
    
    begin
        
        if(rising_edge(clk))                    --on a rising clock edge
            then count := count + 1;            --increment the count
        end if;                

        --Reset the count variable at the end of the ccount
        if(count >= 25000000)
            then
                count := 0;                     --Reset the count                                
                out_flag := not out_flag;       --Invert the output flag
        end if;        

        clk_out <= out_flag;        --Write the clock flag to the output port                 
            
    end process;
end Behavioral;

硬件实现的VHDL代码

--Libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


--Declaration of hardware code
entity HW2_3_Hardware is
    Port(
            sw              : in std_logic_vector (15 downto 0);
            CLK100MHZ       : in std_logic;
            LED             : out std_logic_vector (15 downto 0));
end HW2_3_Hardware;

--Implementation of hardware code
architecture struct of HW2_3_Hardware is
    
    component HW2_3
        port(
            clk         :   in std_logic ;      --100MHz clock input
            clk_out     :   out std_logic);      --Divided clock output
    end component;   
    
begin
    
    LED(1) <= sw(0);    --LED on/off control to confirm the program is operating
    clk_test_1: HW2_3 port map( clk => CLK100MHZ, clk_out => LED(0));           --Run the clock divider component
        
end struct;

我试过以下方法： 使用我通过搜索找到的不同时钟约束变化 将计数变量更改为无符号 将计数器目标更改为更大的值