进位先行加法器的多个驱动程序网络错误 - SystemVerilog

Question

我刚刚开始学习 SystemVerilog，现在正在尝试编写进位前瞻加法器。但是，对于我拥有的

C

信号，我不断收到“多个驱动程序网络”错误。

错误是这样的：

[DRC MDRV-1] Multiple Driver Nets: Net C[0] has multiple drivers: F_OBUF[1]_inst_i_2/O, and F_OBUF[1]_inst_i_3/O.

这是我的顶级模块

Adder

：

`timescale 1ns / 1ps

module Adder (
    input wire[3:0] A,
    input wire[3:0] B,
    input wire Cin,
    output wire[3:0] F,
    output wire Cout
    );

    wire[3:0] P, G; // Propagate and Generate signals
    wire[2:0] C;    // Carry signals

    // Generate propagate (P) and generate (G) signals
    assign P = A ^ B;
    assign G = A & B;

    // Generate carry-out signals using carry-lookahead logic
    assign C[0] = G[0] | (P[0] & Cin);
    assign C[1] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & Cin);
    assign C[2] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & Cin);

    // Instantiate full adders with carry-lookahead logic
    full_adder adder0 (
        .A(A[0]),
        .B(B[0]),
        .Cin(Cin),
        .F(F[0]),
        .Cout(C[0])
    );

    full_adder adder1 (
        .A(A[1]),
        .B(B[1]),
        .Cin(C[0]),
        .F(F[1]),
        .Cout(C[1])
    );

    full_adder adder2 (
        .A(A[2]),
        .B(B[2]),
        .Cin(C[1]),
        .F(F[2]),
        .Cout(C[2])
    );

    full_adder adder3 (
        .A(A[3]),
        .B(B[3]),
        .Cin(C[2]),
        .F(F[3]),
        .Cout(Cout)
    );

endmodule

这是 full_adder 模块：

module full_adder(A, B , Cin, F, Cout);
    input wire A, B, Cin;
    output wire F, Cout;

    assign F = A ^ B ^ Cin;
    assign Cout = (A & B) | (Cin & (A ^ B));
endmodule

如果您能帮助解决此错误，我将不胜感激。

Answer 1

这是

C[0]

的一位司机：

assign C[0] = G[0] | (P[0] & Cin);

这是另一位司机：

    .Cout(C[0])

您必须更改代码，以便

C[0]

只有一名驱动程序。