BDC转7段解码器缺少VCD文件[重复]

Question

当我将这段代码运行到 EDAplayground 时，它会给我一个错误：

Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?

//Verilog模块。

module segment7(bcd,seg); 

        input [3:0] bcd;
        output [6:0] seg;
        reg [6:0] seg;
    always @(bcd)
    begin
        case (bcd) //case statement
            0 : seg = 7'b0000001;
            1 : seg = 7'b1001111;
            2 : seg = 7'b0010010;
            3 : seg = 7'b0000110;
            4 : seg = 7'b1001100;
            5 : seg = 7'b0100100;
            6 : seg = 7'b0100000;
            7 : seg = 7'b0001111;
            8 : seg = 7'b0000000;
            9 : seg = 7'b0000100;
            
            default : seg = 7'b1111111; 
        endcase
    end
    
endmodule

测试台：

module tb_segment7;

    reg [3:0] bcd;
    wire [6:0] seg;
    integer i;

    segment7 uut (.bcd(bcd), .seg(seg));

    initial begin
        for(i = 0;i < 16;i = i+1) //run loop for 0 to 15.
        begin
            bcd = i; 
            #10; //wait for 10 ns
        end     
    end
endmodule

Answer 1

将此初始块添加到测试台，以加载查看波形所需的文件。

module tb_segment7;

  // other stuff

  // add me
  initial
    begin
      $dumpfile("dump.vcd"); 
      $dumpvars;
    end
  
endmodule

参见加载波

或者， 取消选中“运行后打开 EPWaves”框，删除 $dumpfile 和 $dumpvars， 并使用 $monitor 打印要检测的变量（而不是使用waves）。 $monitor 语句在其参数发生更改时打印。
像这样：

module tb_segment7;

  // more stuff
    
  // 
  //initial
  //  begin
  //    $dumpfile("dump.vcd"); 
  //    $dumpvars;
  //  end
  
  // add me instead
  initial
    $monitor("bcd=%h, seg=%h",bcd,seg);
  
endmodule

产生输出：

bcd=0, seg=01
bcd=1, seg=4f
bcd=2, seg=12
bcd=3, seg=06
bcd=4, seg=4c
bcd=5, seg=24
bcd=6, seg=20
bcd=7, seg=0f
bcd=8, seg=00
bcd=9, seg=04
bcd=a, seg=7f
bcd=b, seg=7f
bcd=c, seg=7f
bcd=d, seg=7f
bcd=e, seg=7f
bcd=f, seg=7f