错误：“赋值语句左值中的语法。”尝试在always块中分配reg时

Question

我正在尝试对电路进行建模。这是我正在尝试构建的电路的代码。我在

always

块内，特别是在案例内收到错误。我正在尝试将

reg

NextState

分配给特定状态； 但是我收到错误。

module seq(x_in,y_out,Clk,reset);
    input x_in ,Clk, reset;
    output reg y_out;
    reg  [1:0]NextState;
    reg [1:0]CurrentState;

    parameter stateA = 2'b00,
              stateB = 2'b01,
              stateC = 2'b10,
              stateD = 2'b11;

    always @(x_in or CurrentState) begin
        NextState = stateA;
        y_out = 1'b0;

        case(CurrentState)
           a : begin
            if(x_in) 
             NextState = stateC;
             y_out = 1'b0;
            else
             NextState = stateB;
             y_out = 1'b1; 
           end
           b : begin
            if(x_in)
             NextState = stateD;
             y_out = 1'b1;
            else
             NextState = stateC;
             y_out = 1'b0;
           end
           c : begin
            if(x_in)
             NextState = stateD;
             y_out = 1'b1;
            else
             NextState = stateB ;
             y_out = 1'b0;
           end
           d : begin
            if(x_in)
             NextState = stateA;
             y_out = 1'b0;
            else
             NextState = stateC;
             y_out = 1'b1;
           end
           default : begin
             y_out = 1'bx;
             NextState = 2'bxx;
           end
        endcase
    end

    always @(negedge reset ,posedge Clk) begin
     if(!reset)
     CurrentState <= stateA;
     else
     CurrentState <= NextState;
    end
    
endmodule

在编译过程中，我在

always

块内的多行中收到标题中描述的错误。

seq.v:22: syntax error
seq.v:23: Syntax in assignment statement l-value.
seq.v:30: syntax error
seq.v:31: Syntax in assignment statement l-value.
seq.v:38: syntax error
seq.v:39: Syntax in assignment statement l-value.
seq.v:46: syntax error
seq.v:47: Syntax in assignment statement l-value.
Compilation finished with exit code 8

Answer 1

您有两种类型的语法错误。

您在每个

begin/end

项目的

if/else

语句中缺少

case

关键字。

您的

case

项目使用未声明的标识符：

a

而不是

stateA

。

例如更改：

    case(CurrentState)
       a : begin
        if(x_in) 
         NextState = stateC;
         y_out = 1'b0;
        else
         NextState = stateB;
         y_out = 1'b1; 
       end

至：

    case(CurrentState)
       stateA : begin
        if(x_in) begin       // add begin
         NextState = stateC;
         y_out = 1'b0;
        end else begin      // add begin and end
         NextState = stateB;
         y_out = 1'b1; 
        end                 // add end
       end

---

iverilog

错误不是很具体。您通常可以在不同的模拟器上得到更有意义的错误，例如 EDA Playground

上的错误