Verilog 错误：无法由原语或连续赋值驱动

Question

我正在尝试在 Verilog 中创建状态机，但收到错误：

error: reg state; cannot be driven by primitives or continuous assignment.
 error: Port 6 (state) of mealy_machine is connected to state.

它说错误出现在我的测试平台的第 8 行，因此是 mealy_machine M1 的实例调用。

module mealy_machine(F, clk, inbits, clear, preset, state);
input clk, inbits, clear, preset;
output reg F;
output reg [1:0] state;

initial begin
  assign state = 2'b00;
end

always @ (posedge clk)
begin //always
    if (clear == 1 && preset == 1)
    begin //if
        begin //case
            case(state)

            2'b00:
            if(inbits)
            begin
                assign state = 2'b00;
                assign F = 1'b1;
            end
            else
            begin
                assign state = 2'b01;
                assign F = 2'b00;
            end


            2'b01:
            if(inbits)
            begin
                assign state = 2'b11;
                assign F = 2'b00;
            end
            else
            begin
                assign state = 2'b10;
                assign F = 2'b01;
            end


            2'b10:
            if(inbits)
            begin
                assign state = 2'b01;
                assign F = 2'b00;
            end
            else
            begin
                assign state = 2'b00;
                assign F = 2'b01;
            end


            2'b11:
            if(inbits)
            begin
                assign state = 2'b10;
                assign F = 2'b01;
            end
            else
            begin
                assign state = 2'b11;
                assign F = 2'b00;
            end
            endcase
        end
    end
    else
    begin
        state <= 2'b00;
        F <= 2'b00;
        if(clear == 0 && preset == 1) 
        begin
            assign state = 2'b00;
            assign F = 2'b00;
        end
        else if (clear == 1 && preset == 0)
        begin
            assign state = 2'b11;
            assign F = 2'b01;
        end
        else if (clear == 1 && preset == 1)
        begin
            assign state = 2'b00;
           assign F = 2'b00;
        end
    end
end
endmodule

`include "mealy_machine.v"

module mealy_machine_tb();
reg clk, clear, inbits, preset;
reg [1:0] state;
wire F;

mealy_machine M1(F, clk, inbits, clear, preset, state);

initial begin


    $dumpfile("mealy_machine_tb.vcd");
    $dumpvars(0, mealy_machine_tb);
    #10;
    clk = ~ clk;

    #10;
    assign state = 2'b00;
    assign inbits = 2'b00;

    #10;
    assign state = 2'b01;
    assign inbits = 2'b00;

    #10;
    assign state = 2'b10;
    assign inbits = 2'b00;

    #10;
    assign state = 2'b11;
    assign inbits = 2'b00;

    #10;
    assign state = 2'b00;
    assign inbits = 2'b01;

    #10;
    assign state = 2'b01;
    assign inbits = 2'b01;

    #10;
    assign state = 2'b10;
    assign inbits = 2'b01;

    #10;
    assign state = 2'b11;
    assign inbits = 2'b01;

end
endmodule

我读到，将状态从 reg 更改为wire 可能会有所帮助，但它给了我一大堆错误，指出测试台中状态变量的每个分配语句“state 不是 mely_machine-tb 中的有效左值”

Answer 1

您的代码中有多个语法错误：

• 您不应将 testbnech 中的

  state

  信号声明为

  reg

  并尝试为其分配任何值，因为它是

  mealy_machine

  实例的输出端口。
• 您在两个模块中都滥用了

  assign

  关键字。没有必要。

此代码编译时没有语法错误：

module mealy_machine(F, clk, inbits, clear, preset, state);
input clk, inbits, clear, preset;
output reg F;
output reg [1:0] state;

always @ (posedge clk)
begin //always
    if (clear == 1 && preset == 1)
    begin //if
        begin //case
            case(state)

            2'b00:
            if(inbits)
            begin
                state = 2'b00;
                F = 1'b1;
            end
            else
            begin
                state = 2'b01;
                F = 2'b00;
            end


            2'b01:
            if(inbits)
            begin
                state = 2'b11;
                F = 2'b00;
            end
            else
            begin
                state = 2'b10;
                F = 2'b01;
            end


            2'b10:
            if(inbits)
            begin
                state = 2'b01;
                F = 2'b00;
            end
            else
            begin
                state = 2'b00;
                F = 2'b01;
            end


            2'b11:
            if(inbits)
            begin
                state = 2'b10;
                F = 2'b01;
            end
            else
            begin
                state = 2'b11;
                F = 2'b00;
            end
            endcase
        end
    end
    else
    begin
        state <= 2'b00;
        F <= 2'b00;
        if(clear == 0 && preset == 1) 
        begin
            state = 2'b00;
            F = 2'b00;
        end
        else if (clear == 1 && preset == 0)
        begin
            state = 2'b11;
            F = 2'b01;
        end
        else if (clear == 1 && preset == 1)
        begin
            state = 2'b00;
           F = 2'b00;
        end
    end
end
endmodule


module mealy_machine_tb();
reg clk, clear, inbits, preset;
wire [1:0] state;
wire F;

mealy_machine M1(F, clk, inbits, clear, preset, state);

always #10 clk = ~ clk;

initial begin
    $dumpfile("mealy_machine_tb.vcd");
    $dumpvars(0, mealy_machine_tb);
    clk=0;
    #10;

    #10;
    inbits = 2'b00;

    #10;
    inbits = 2'b00;

    #10;
    inbits = 2'b00;

    #10;
    inbits = 2'b00;

    #10;
    inbits = 2'b01;

    #10;
    inbits = 2'b01;

    #10;
    inbits = 2'b01;

    #10;
    inbits = 2'b01;

end
endmodule

我还将测试台中的

clk

信号移至其自己的

always

块，因为它始终未知。