我正在编写一个i2c主模块,并且我有Microchip提供的AT24C02D的verilog模型用于测试平台,我在代码中看到一些“->”,这是什么意思? 参考:https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/BoardDesignFiles/AT24C02D.v
//************************************************************************
//********************* S_START and S_STOP conditions ********************
//************************************************************************
// Start trigger allows latency between start condition and falling edge
// of SCL. If stop occurs in this interval the machine ignores the start
// condition and awaits a subsequent start condition.
// START Condition Detection
always @ (negedge SDA_in)
if(SCL == 1) begin
if (VERBOSE) $display("START condition detected", $time);
S_STOP = 0;
S_START = 1;
-> START_condition; // Start condition event
if (VERBOSE) $display ("Got START condtion event");
@(STOP_condition or negedge SCL)
if (SCL == 0) begin
if (VERBOSE) $display ("First negedge of SCL after START", $time);
Valid_Address_flag = 0;
if(VERBOSE) $display("START event triggered");
-> START_trigger; // Start trigger event
@ (posedge SCL) S_START = 0; // Waits until cycle ends
end
else begin // STOP condition detected under same clock
if (VERBOSE) $display ("STOP under same clock as START");
S_START = 0;
S_STOP = 1;
end
end
我成功地用iverilog编译了该文件。
在链接中的
AT24C02D.v
文件中,我搜索了START_condition
并在第535行发现了这个event
声明:
event START_condition;
->
语法用于触发事件。