我正在尝试从DDR3 ram读取和写入，连接到我的FPGA Artix-7。我正在使用MIG-7，在Vivado 2015.1中构建我的IP。
IP需要有两个输入时钟，参考时钟和系统时钟。我使用内部IP（FPGA内部PLL）制作400 Mhz时钟，并将时钟连接到它们。
电路不起作用，ui_clk_sync_rst为'0'，init_calib_complete永远不会变高！
我该如何分配这些时钟信号？
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity Main_Prg is
Port (
-- Inouts
ddr3_dq : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(0 downto 0);
ddr3_dqs_n : inout std_logic_vector(0 downto 0);
-- Outputs
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
LEDV6 : out STD_LOGIC;
LEDV7 : out STD_LOGIC;
clk25 : in STD_LOGIC);
end Main_Prg;
architecture Behavioral of Main_Prg is
component Clock_IP
port
(
clk_in : in std_logic;
clk_out : out std_logic
);
end component Clock_IP;
component DDR3_RAM
port(
ddr3_dq : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(0 downto 0);
ddr3_dqs_n : inout std_logic_vector(0 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
-- Reference Clock Ports
clk_ref_i : in std_logic;
sys_rst : in std_logic
);
end component DDR3_RAM;
signal cntr01 : std_logic_vector(50 downto 0) := (others=>'0');
signal cntr02 : std_logic_vector(50 downto 0) := (others=>'0');
signal ck25 : std_logic ;
signal ck400 : std_logic ;
signal app_addr : std_logic_vector(27 downto 0) := (others=>'0') ;
signal app_cmd : std_logic_vector(2 downto 0) := (others=>'0') ;
signal app_en : std_logic := '0';
signal app_wdf_data : std_logic_vector(63 downto 0) := (others=>'0') ;
signal app_wdf_end : std_logic := '0';
signal app_wdf_wren : std_logic := '0';
signal app_rd_data : std_logic_vector(63 downto 0) := (others=>'0') ;
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal clk : std_logic;
signal rst : std_logic;
signal init_calib_complete_s : std_logic;
signal app_rdy_i : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_rd_data_valid_i : std_logic;
signal init_calib_complete_i : std_logic;
signal app_addr_i : std_logic_vector(27 downto 0) := (others=>'0') ;
begin
ck25 <= clk25 ;
U1: process(clk)
begin
if rising_edge(clk) then
cntr01 <= cntr01 + 1 ;
end if;
end process;
--U2: process(ck400)
--begin
-- if rising_edge(ck400) then
-- if cntr02(28) = '0' then
-- cntr02 <= cntr02 + 1 ;
-- end if;
-- end if;
--end process;
Uclk: Clock_IP port map
( clk_in => ck25,
clk_out=> ck400);
LEDV6 <= init_calib_complete_i ; -- cntr01(25);
LEDV7 <= cntr01(25);
u_DDR3_RAM : DDR3_RAM
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
init_calib_complete => init_calib_complete_s,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
-- System Clock Ports
sys_clk_i => ck400,
-- Reference Clock Ports
clk_ref_i => ck400,
sys_rst => cntr02(28)
);
-- End of User Design top instance
end Behavioral;
无法在FPGA下生成sys_clk。你必须从外部振荡器提供它。按照AC701 Artix7 kit的例子，它使用200Mhz的差分时钟。
如果您的ocsillator不适合您的MIG，您可以创建一个带有两个输出的时钟（来自时钟向导），然后将第一个时钟连接到MIG的系统时钟，将第二个时钟连接到参考时钟。
在MIG的设置中，参考和系统时钟必须设置为“无缓冲”类型。
参考时钟必须为200 MHz。如果系统时钟为200 MHz，则可以选择“使用系统时钟”。