我正在尝试使用 lfsr 的输出作为 2 位全进位加法器的输入。
我在
rnd_word(0) = > rnd_bit
上收到这个错误:
错误 (10500):somma_compl2.vhd(62) 文本“>”附近的 VHDL 语法错误;期待“(”,或标识符,或一元运算符
library ieee;
use ieee.std_logic_1164.all;
entity RippleAdder is
port (a : in std_logic_vector(1 downto 0);
b : in std_logic_vector(1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(2 downto 0);
ck_1 : in std_logic
);
end RippleAdder;
-- Ripple Carry Adder description using component instantiation statements
architecture structural of RippleAdder is
component LFSR
generic(
width: positive := 2; -- dimensione del LFSR
bit_config: natural -- configurazione del LFSR
);
port(
ck : in std_logic; -- clock
rst: in std_logic; -- reset
rnd_word: out std_logic_vector(0 to width-1) -- parola pseudo-casuale
);
end component;
SIGNAL rnd_bit : std_logic;
component adder
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end component;
SIGNAL cout1 : std_logic;
begin
dut_lfsr: lfsr
port map(
ck => ck_1,
rst => '1', --active low
rnd_word(0) = > rnd_bit
);
-- component instantiation
dut_adder1: adder
PORT MAP (a => rnd_bit,
b => b(0),
cin => cin,
sum => sum(0),
cout => cout1);
--a => a(0),
--b => b(0),
--cin => cin,
--sum => sum(0),
--cout => cout1);
dut_adder2: adder
PORT MAP (a => a(1),
b => b(1),
cin => cout1,
sum => sum(1),
cout => sum(2));
end structural;
我尝试了其他方法,比如在 std_logic_vector 中同时使用 rnd_word 和 rnd_bit
像这样使用它们:
dut_lfsr: lfsr
port map(
ck => ck_1,
rst => '1',
rnd_word(0) = > rnd_bit(0)
);
但我仍然得到同样的错误