为什么我的代码在运行时会返回这个错误

Question

library IEEE; 

use IEEE.std_logic_1164.all; 

entity LogicC is  

port(TL,TS,RL,GL,YL,TRX,CLK:in std_logic_vector(1 downto 0);O:out std_logic_vector(1 downto 0));

end entity; 

architecture DigitalS of LogicC is 

begin  

process(TL,TS,GL,YL,RL,TRX,O,CLK) 

begin 

if CLK = '1' and CLK'event then  

case O is 

when "000" => if TL='1'then O <= "000"; 

              elsif TL ='1' and TS = '0' and RL = '0' and TRX = '1' then O <= "001"; 

              end if; 

when "001" => if TL= '0' then O <= "001"; 

              elsif TL ='0' and TS = '1' and RL = '0' and TRX = '1' then O <= "011"; 

              end if; 

when "011" => if TS= '0' then O <= "011"; 

              elsif TL='0' and TS='1' or GL='1' and TRX= '1' then O <= "010"; 

              end if; 

when "010" => if TS='1' and YL='1' then O <= "010"; 

              elsif TL='1' and TS= '0' or YL='1' and TRX= '1' then O <= "100"; 

              end if; 

when "100" => if TS = '1' and RL= '1' then O <= "100"; 

              elsif TL='1' and TS='0' or RL= '0'  and TRX= '0' then O <= "101"; 

              end if; 

when "101" => if TL='0' and TS='0' or RL='0' and TRX='0' then O <= "111"; 

              elsif TL='1' and RL='1' then O <= "101"; 

              end if; 

when "111" => if TL= '1' and GL='1' then O <= "111"; 

              elsif TL='0' and TS='0' or GL= '1' and TRX = '0' then "110"; 

              end if; 

when "110" => if TL='0' and TS='1' then O <= "110"; 

              elsif TL='1' and TS='0' or YL='1' and TRX='0' then "000"; 

              end if; 

end case; 

end if; 

end process; 

end architecture DigitalS of LogicC; 

我试图将它放入 VHDL 工具中进行尝试并修复代码中的任何错误，但我总是以同样的事情结束：

第 77 行第 27 行：意外的 'o' 期待 "--"、"/*"、';' 或白色 空间

当我尝试运行它时。关于如何修复我的代码的任何建议都会有所帮助。

Answer 1

and

和

or

运算符具有相同的优先级。所以当你有这样的事情时：

elsif TL='0' and TS='1' or GL='1' and TRX= '1' then

编译器不知道你是不是这个意思：

elsif (TL='0' and TS='1') or (GL='1' and TRX= '1') then

或者这个

elsif TL='0' and (TS='1' or GL='1') and TRX= '1' then

所以你需要向编译器澄清你的意思。

还有其他问题：

• 您的案例陈述并未涵盖所有可能的选项。我建议一个

  when others =>

  案例。

• end architecture digitalS

  ，你不能有

  of logicC