我在VHDL中制作通用的N位ALU。我无法为进位添加值,或借用减法。我尝试过以下方法:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
generic(n: integer :=1); --Default to 1
port (
a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
op : in std_logic_vector(1 downto 0);
output : out std_logic_vector(n-1 downto 0);
carryborrow: out std_logic
);
end alu;
architecture Behavioral of alu is
signal result: std_logic_vector(n downto 0);
begin
process( a, b, op )
begin
case op is
when "00" =>
result(n) <= '0';
result(n-1 downto 0) <= a and b; --and gate
output <= result(n-1 downto 0);
carryborrow <= '0';
when "01" =>
result(n) <= '0';
result(n-1 downto 0) <= a or b; --or gate
output <= result(n-1 downto 0);
carryborrow <= '0';
when "10" =>
result(n) <= '0';
result(n-1 downto 0) <= std_logic_vector(signed(a) + signed(b)); --addition
output <= result(n-1 downto 0);
carryborrow <= result(n);
when "11" =>
result(n) <= '0';
result(n-1 downto 0) <= std_logic_vector(signed(a) - signed(b)); --subtraction
output <= result(n-1 downto 0);
carryborrow <= result(n);
when others =>
NULL;
end case;
end process;
end Behavioral;
这似乎将carryborrow
位设置为始终为0.如何在没有类型错误的情况下将其分配给它应该是什么?
您的代码中存在错误:
i)您没有考虑到信号不会立即更新的事实。因此,以下几行不会像我想的那样做:
result(n) <= '0';
result(n-1 downto 0) <= a and b; --and gate
output <= result(n-1 downto 0);
相反,您需要在组合过程之外使用驱动output
和carryborrow
的线,如下所示。 ii)假设您希望此代码是可合成的,只需将NULL
放入您的always分支将导致锁定被推断。你也需要在其他分支中驾驶result
。
因此,假设你的进位输出如何使用and
和or
操作,这就是我编写代码的方式:
architecture Behavioral of alu is
signal result: std_logic_vector(n downto 0);
begin
process( a, b, op )
begin
case op is
when "00" =>
result <= '0' & (a and b); --and gate
when "01" =>
result <= '0' & (a or b); --or gate
when "10" =>
result <= std_logic_vector(resize(signed(a), n+1) + resize(signed(b), n+1)); --addition
when "11" =>
result <= std_logic_vector(resize(signed(a), n+1) - resize(signed(b), n+1)); --subtraction
when others =>
result <= (others => 'X');
end case;
end process;
output <= result(n-1 downto 0);
carryborrow <= result(n);
end Behavioral;
我通常这样做:
result <= std_logic_vector(signed(a(n-1) & a) + signed(b(n-1) & b));
result <= std_logic_vector(signed(a(n-1) & a) - signed(b(n-1) & b));
符号扩展然后执行操作以处理溢出,当结果是一个额外的位长。
嗯,在4位环境中考虑一下,比如a="0101"
和b="1001"
。添加它们应该给output="1110"
,没有携带。
然而,与resize(signed(a), n+1)
和resize(signed(b), n+1)
延伸的标志将设置a="00101"
和b="11001"
,因此result="11110"
和carryborrow='1'
,这是错误的!
通过符号扩展矢量a
和b
,数字范围增加到5位,因此result
需要6位才能保持进位,我们回到正方形。矢量a
和b
应该只是零扩展,即'0' & a
和'0' & b
,然后将它们添加到result
,然后carryborrow
,作为result
的MSB(最重要位),将获得正确的值。