我正在尝试使用 Intel 提供的 tcl 脚本运行 IntelFPGA 的示例设计。它报告“错误（vlog-7）无法在读取模式下打开单元文件“blabla”。没有这样的文件或目录（errno = ENOENT）。我找不到错误。然后我尝试了我之前使用的modelsim项目，它曾经可以工作。我犯了同样的错误！可能出了什么问题？
global env ;
# set QUARTUS_INSTALL_DIR "$env(QUARTUS_ROOTDIR)" => initially i thought
# there is something wrong with the rootdir, so i changed to the row
# below:
set QUARTUS_INSTALL_DIR "C:/intelFPGA/18.0/quartus"
set SETUP_SCRIPTS ../setup_scripts
set tb_top_waveform msim_wave.do
set QSYS_SIMDIR "./../setup_scripts"
set TOP_LEVEL_NAME tb_top
source $SETUP_SCRIPTS/mentor/msim_setup.tcl
# Compile device library files
dev_com
================================================== => dev_com，这是第29行，这里出现错误，见下文
modelsim 报告：
Modelsim> VHDL 2008 do tb_run.tcl
# C:/intelFPGA/18.0/quartus
# ../setup_scripts
# msim_wave.do
# ./../setup_scripts
# tb_top
# [exec] file_copy
# List Of Command Line Aliases
#
# file_copy -- Copy ROM/RAM files to simulation directory
#
# dev_com -- Compile device library files
#
# com -- Compile the design files in correct order
#
# elab -- Elaborate top level design
#
# elab_debug -- Elaborate the top level design with novopt option
#
# ld -- Compile all the design files and elaborate the top level design
#
# ld_debug -- Compile all the design files and elaborate the top level design with -novopt
#
#
#
# List Of Variables
#
# TOP_LEVEL_NAME -- Top level module name.
# For most designs, this should be overridden
# to enable the elab/elab_debug aliases.
#
# SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module.
#
# QSYS_SIMDIR -- Qsys base simulation directory.
#
# QUARTUS_INSTALL_DIR -- Quartus installation directory.
#
# USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases.
#
# USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases.
#
# USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases.
#
# USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases.
#
# SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script.
#
# FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always.
# [exec] dev_com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 10:43:14 on Jun 25,2019
# vlog -reportprogress 300 C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v -work altera_ver
# ** Error: (vlog-7) Failed to open design unit file "C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 10:43:14 on Jun 25,2019, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.
# Error in macro ./tb_run.tcl line 29
# C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.
# while executing
# "vlog C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v -work altera_ver"
# ("eval" body line 1)
# invoked from within
# "eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" ..."
# invoked from within
# "if [string is false -strict [modelsim_ae_select $FORCE_MODELSIM_AE_SELECTION]] {
# eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_CO..."
# ("eval" body line 5)
# invoked from within
# "dev_com "
真的不知道你是如何通过重新启动来解决这个问题的。这是最有可能出现的问题以及我是如何解决的。
我们对这个问题有一个声明： vlog-7 错误。无法以读取模式打开设计单元文件
我太关注“读取模式”并试图弄清楚为什么禁止启动声明的操作。 然而，最有可能的问题是您在发生警告的目录中并没有真正的实际文件。
然后我意识到我最终更改了文件夹的名称，因此无法读取该文件。看一下您在 tcl、.do 和项目文件之前没有对路径进行任何更改。
我的问题是项目文件是只读的，导致无法写入新路径，所以找不到文件。
检查此问题的快速方法是将路径复制到文件夹 windows，然后按 Enter