在VHDL架构声明区域中,我有时会使用像
for and_gate_inst : and_gate use entity work.and_gate(rtl);
这样的嵌入式配置,但我不知道当实例位于生成内部时如何编写此嵌入式配置。也许这不受支持。我的代码示例中的嵌入式配置语句产生错误并且不正确:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (
inp1_i, inp2_i : in std_logic;
out_o : out std_logic
);
end entity;
architecture rtl of and_gate is
begin
out_o <= inp1_i and inp2_i;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity embedded_conf is
end entity embedded_conf;
library work;
architecture struct of embedded_conf is
signal inp1, inp2, out1 : std_logic;
component and_gate is
port (
inp1_i : in std_logic;
inp2_i : in std_logic;
out_o : out std_logic
);
end component;
for dummy_g for and_gate_inst : and_gate use entity work.and_gate(rtl); -- Not correct!!!
begin
dummy_g: if true generate
and_gate_inst : and_gate
port map (
inp1_i => inp1,
inp2_i => inp2,
out_o => out1
);
end generate dummy_g;
end architecture;
有人知道这个嵌入式配置是什么样子吗?
配置规范(例如 IEEE 1076-2008 7.3 配置规范)是一个块声明项,可以在架构声明部分(3.3.2 架构声明部分)中找到:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (
inp1_i, inp2_i: in std_logic;
out_o: out std_logic
);
end entity;
architecture rtl of and_gate is
begin
out_o <= inp1_i and inp2_i;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity embedded_conf is
end entity embedded_conf;
-- library work;
architecture struct of embedded_conf is
signal inp1, inp2, out1: std_logic;
component and_gate is
port (
inp1_i: in std_logic;
inp2_i: in std_logic;
out_o: out std_logic
);
end component;
-- for dummy_g
-- for and_gate_inst and_gate
-- use entity work.and_gate(rtl); -- Not correct!!!
begin
dummy_g:
if true generate
for and_gate_inst: and_gate
use entity work.and_gate(rtl);
begin
and_gate_inst:
and_gate
port map (
inp1_i => inp1,
inp2_i => inp2,
out_o => out1
);
end generate dummy_g;
end architecture;
无法在配置规范中指定层次结构(没有 for for)。为此,您需要一个配置声明,它是一个主要单元,并且是 ghdl 详细阐述 (-e) 和模拟 (-r) 的目标。
注意,当使用保留字实体时,只有一种可能的绑定指示:
-- library work;
architecture struct of embedded_conf is
signal inp1, inp2, out1: std_logic;
component and_gate is
port (
inp1_i: in std_logic;
inp2_i: in std_logic;
out_o: out std_logic
);
end component;
-- for dummy_g
-- for and_gate_inst and_gate
-- use entity work.and_gate(rtl); -- Not correct!!!
begin
dummy_g:
if true generate
-- for and_gate_inst: and_gate
-- use entity work.and_gate(rtl);
-- begin
and_gate_inst:
and_gate
port map (
inp1_i => inp1,
inp2_i => inp2,
out_o => out1
);
end generate dummy_g;
end architecture;
configuration embedded_conf_configuration of embedded_conf is
for struct
for dummy_g
for and_gate_inst: and_gate
use entity work.and_gate(rtl);
end for;
end for;
end for;
end embedded_conf_configuration;
调用方式如下:
%: ghdl -e embedded_conf_configuration
%: ghdl -r embedded_conf_configuration
%:
将 ghdl 与 gcc 或 llvm 后端结合使用。对于 mcode 版本,在所有设计单元都被分析到一个或多个库后,只需 -r 即可。
另请注意,用于 FPGA 综合的综合工具链很少支持配置声明,而这是 IEEE Std 1076.6-2004 RTL 综合中的要求(由于缺乏供应商参与而被撤回)。
配置声明中的块配置也可以嵌套:
configuration test_config of des_test is
for behave
for des_chip: des
use configuration work.behave_config;
end for;
end for;
end test_config;