prbs_verify_tb.vhd(45)：靠近“进程”：(vcom-1576) 期待开始

Question

我对 VHDL 编码比较陌生，目前在编译过程中遇到了问题。我将非常感谢任何帮助解决此错误。该测试平台是涉及伪随机二进制序列 (PRBS) 生成器的项目的一部分。下面是我的代码片段和具体的错误消息：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prbs_verify_tb is
end prbs_verify_tb;

architecture testbench of prbs_verify_tb is
  signal clk, reset, load, en, pass : std_logic;
  signal data_in_hex, data_out_hex : std_logic_vector(3 downto 0);
  signal addr : std_logic_vector(4 downto 0) := "00000";
  signal data_in : std_logic;

  constant CLK_PERIOD : time := 10 ns; -- Adjust as needed
  constant SIMULATION_TIME : time := 500 ns; -- Adjust as needed

  -- Component instantiation
  COMPONENT prbs_verify
    Port (
      clk      : in std_logic;
      reset    : in std_logic;
      load     : in std_logic;
      en       : in std_logic;
      pass     : out std_logic
    );
  end COMPONENT;

  -- Component instantiation for ROMs
  COMPONENT PRBS_Verifier_ROM_input
    Port (
      addr      : in std_logic_vector(4 downto 0);
      input_out : out std_logic_vector(3 downto 0)
    );
  end COMPONENT;

  COMPONENT PRBS_Verifier_ROM_output
    Port (
      addr      : in std_logic_vector(4 downto 0);
      input_out : out std_logic_vector(3 downto 0)
    );
  end COMPONENT;

  -- Clock generation process
  process
  begin
    clk <= '0';
    wait for CLK_PERIOD / 2;
    clk <= '1';
    wait for CLK_PERIOD / 2;
  end process;

  -- Stimulus process
  process
  begin
    wait for CLK_PERIOD;
    
    reset <= '1';
    wait for CLK_PERIOD;
    reset <= '0';
    wait for CLK_PERIOD;

    -- Test case 
    load <= '1';
    en <= '1';
    wait for CLK_PERIOD * 10; -- cycles for loading
    load <= '0';
    wait for CLK_PERIOD * 100; -- Run for some cycles
    en <= '0';
    wait for CLK_PERIOD * 10; --  cycles for checking result

    wait for SIMULATION_TIME - CLK_PERIOD * 120;
  end process;

  -- Instantiate components
  signal prbs_pass : std_logic;
  signal prbs_output : std_logic;

  signal prbs_verify_rom_input : std_logic_vector(3 downto 0);
  signal prbs_verify_rom_output : std_logic_vector(3 downto 0);

begin
  prbs_verify_inst : prbs_verify
    port map (
      clk      => clk,
      reset    => reset,
      load     => load,
      en       => en,
      pass     => prbs_pass
    );

  prbs_verify_rom_input_inst : PRBS_Verifier_ROM_input
    port map (
      addr      => addr,
      input_out => prbs_verify_rom_input
    );

  prbs_verify_rom_output_inst : PRBS_Verifier_ROM_output
    port map (
      addr      => addr,
      input_out => prbs_verify_rom_output
    );

  -- Check if prbs_verify output matches ROM output
  prbs_output <= prbs_pass and (prbs_verify_rom_input = prbs_verify_rom_output);

  -- Assertions
  assert (prbs_output = '1') report "PRBS verification failed!" severity failure;

  wait for SIMULATION_TIME;
  report "Simulation completed" severity note;
end testbench;

错误信息：

prbs_verify_tb.vhd(45): near "process": (vcom-1576) expecting BEGIN.

谢谢你

Answer 1

在VHDL中，process语句后面应该跟is关键字，而不是begin。

  -- Clock generation process
  process
  begin
    clk <= '0';
    wait for CLK_PERIOD / 2;
    clk <= '1';
    wait for CLK_PERIOD / 2;
  end process;