使用 VHDL 为 MIPS 处理器设计寄存器文件？

Question

我正在使用 VHDL 设计 MIPS 处理器。在写操作中我遇到了错误，我无法真正理解它的内容。我已经设计了一个 MUX 32*1 , Decoder 5*32 & Flopr.

RegFile

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Project_Package.ALL;

entity Reg is
    Port ( read_sel1 : in  STD_LOGIC_VECTOR (4 downto 0);
           read_sel2 : in  STD_LOGIC_VECTOR (4 downto 0);
           write_sel : in  STD_LOGIC_VECTOR (4 downto 0);
           write_ena : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           write_data : in  STD_LOGIC_VECTOR (31 downto 0);
           data1 : out  STD_LOGIC_VECTOR (31 downto 0);
           data2 : out  STD_LOGIC_VECTOR (31 downto 0));
end Reg;

architecture Behavioral of Reg is

--Signal Declaration
signal decoder_output: STD_LOGIC_VECTOR (31 downto 0);
signal reset_flopr: STD_LOGIC := '0';
type reg_type is array (0 to 31 ) of std_logic_vector (31 downto 0);
signal reg_outputs: reg_type;

begin

-------------------------------------------------------------------------------------------
----------------------------------Write Implementation-------------------------------------
-------------------------------------------------------------------------------------------

--Write Decoder
decoder1: Decoder_5x32 port map (read_sel1,decoder_output);

--Registers
reg_gen : for i in 0 to 31 generate
  reg: Flopr port map (clk, reset_flopr, write_ena AND decoder_output(i), write_data, reg_outputs(i));
end generate reg_gen;


end Behavioral;

包装：

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package Project_Package is

--Flopr Implementation
component Flopr GENERIC(n:integer);
     Port ( CLK : in  STD_LOGIC;
           RST : in  STD_LOGIC;
           Load : in STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (n-1 downto 0);
           Q : out  STD_LOGIC_VECTOR (n-1 downto 0));
end component;

--Decoder Implementation
component Decoder_5x32
    Port ( Selector : in  STD_LOGIC_VECTOR (4 downto 0);
           Data_Out : out  STD_LOGIC_VECTOR (31 downto 0));
end component;

--MUX Implementation
component MUX_32x1
    Port ( Data_In : in  STD_LOGIC_VECTOR (31 downto 0);
           Selector : in  STD_LOGIC_VECTOR (4 downto 0);
           Data_Out : out  STD_LOGIC);
end component;

end Project_Package;

错误：

第 35 行：Formal 没有实际值或默认值。

Answer 1

VHDL保留字

array

只能用于类型声明，不能用于对象声明（

variable

、

signal

、

constant

）。因此，您首先需要声明一个数组类型来保存您的

reg_outputs

：

例如

type reg_array_t is array (0 to 31) of std_logic_vector(31 downto 0);

signal reg_outputs : reg_array_t := (others => (others => '0'));

您还在程序区域之外使用了程序

for

循环（例如

process

、

function

、

procedure

）。在这里，你需要使用一个生成循环：

reg_gen : for i in 0 to 31 generate
  ...
end generate reg_gen;