如何比较 VHDL 中的数组？

Question

我在比较 VHDL 中的数组时遇到问题， 在 SysVerilog 语言中这很容易，但我找不到任何解决方案来解决我的问题，你能帮助我吗？

它表示在数组的特定间隔中使用 other => 1 是非法的。 52 号线。

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 02.10.2023 18:16:34
-- Design Name: 
-- Module Name: RELU - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ReLU is
  generic (
    dataWidth : integer := 16;
    weightIntWidth : integer := 4
  );
  port (
    PIClk : in std_logic;
    PIRELUInput : in std_logic_vector(2*dataWidth-1 downto 0);
    PORELUOut : out std_logic_vector(dataWidth-1 downto 0)
  );
end entity ReLU;

architecture Behavioral of ReLU is

  constant positive_saturate : std_logic_vector(dataWidth-1 downto 0) := (others => '0');

begin

  process(PIClk)
    variable x_signed : signed(2*dataWidth-1 downto 0);
  begin
    if rising_edge(PIClk) then
    
        x_signed := signed(PIRELUInput);
        
      if x_signed >= 0 then
      
        if x_signed(2*dataWidth-1 downto weightIntWidth) = (others => '1') then -- <<<<<HERE
          PORELUOut <= positive_saturate & '1'; -- Positive saturate
        else
          PORELUOut <= PIRELUInput(dataWidth+weightIntWidth-1 downto weightIntWidth);
        end if;
        
      else
          PORELUOut <= (others => '0'); -- Negative input, output is 0
      end if;
      
    end if;
    
  end process;

end  Behavioral;

我尝试过使用其他的，但效果并不好。

Answer 1

正确的是：

if x_signed(2*dataWidth-1 downto weightIntWidth)=
           (2*dataWidth-1 downto weightIntWidth => '1') then