我正在尝试制作4位乘法器。这是我的顶层设计:
这是两个模块:
但是,当我尝试对此进行模拟时,没有任何输出。我的测试台:
ARCHITECTURE behavior OF sim3 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplicator
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
reset : IN std_logic;
clk : IN std_logic;
start : IN std_logic;
prod : OUT std_logic_vector(7 downto 0);
ready : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal start : std_logic := '0';
--Outputs
signal prod : std_logic_vector(7 downto 0);
signal ready : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplicator PORT MAP (
a => a,
b => b,
reset => reset,
clk => clk,
start => start,
prod => prod,
ready => ready
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period;
reset<='1';
wait for clk_period;
reset<='0';
a<="0011";
b<="0010";
start <='1';
wait for clk_period*10;
end process;
END;
当我将开始设置为'1'时,模拟就停止了。我不知道为什么我收到以下错误:
ERROR: at 20 ns(10000): Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value in File "D:/faculta/PL II/multiplicator/reg8.vhd" Line 45. Please correct this code in order to advance past the current simulation time.
<< img src =“ https://image.soinside.com/eyJ1cmwiOiAiaHR0cHM6Ly9pLnN0YWNrLmltZ3VyLmNvbS9WVlk4di5wbmcifQ==” alt =“在此处输入图像描述”>
我看不到那行有什么问题:
q_s <= "00000000" WHEN reset='1' ELSE d WHEN reset='0' and load='1' ELSE q_s;
请帮忙吗?
Google翻译有帮助。似乎没有人为他们的任务提供讲义。
[如果您查看q_s
中对reg4
的分配的原始实现:block1:
block (ck = '1' and not ck'stable)
begin
q_s <= guarded "0000" when reset = '1' else
d when reset = '0' and load = '1' else
q_s;
end block block1;
我将其转换为可综合的过程语句,而不是块语句,明确地reg4
(和reg8
)是一个时钟寄存器:
block1: process (ck) begin if rising_edge(ck) then if reset = '1' then q_s <= (others => '0'); elsif load = '1' then q_s <= d; end if; end if; end process;
原始工作的原因是,块语句可以具有保护语句。
此更改使q_s
成为具有同步复位的时钟寄存器。您可能还会注意到我们不再引用
q_s
,可以直接分配q。在控制状态机中,将
next_state
分配给current_state
的过程同样可以更新:
process (ck) begin if ck'event and ck = '1' then -- or rising_edge(ck) current_state <= next_state; end if; end process;
仅出于可读性。使用
not ck'stable
形式表示时钟事件并不常见,请注意,您似乎也错过了实现reg8
的含义,可能还包括reg4
和automat
。
在IEEE Std 1076.6-2004中证明了保护表达式作为边缘敏感时钟的综合资格,6.1.3.6使用保护块的边缘敏感存储。