我对VHDL和FPGA还是很陌生，并且遇到了麻烦。我目前在zybo z7-10上研究视频过滤器，并开始使用此指南在板上创建HDMI直通：https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10?_ga=2.34188391.796043983.1579510279-2100398226.1578999679
因此，在完成所有工作后，我想要做的就是能够实现视频输出。为此，我尝试将最后8位的rgb 24位向量设置为0，从输出中删除所有蓝色。如果我尝试以下代码（带有或不带有过程块），则在“ if”语句行上会出现语法错误
process is
begin
if sw ='0' then
vid_pData(7 downto 0) <= sw
end if;
end process;
问题是我似乎无法将其放在代码中的任何位置而不会导致错误。有人可以解释这里发生了什么吗？
下面的完整代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity hdmi_pass_top is
Port (
sysclk_i : in std_logic; -- 125MH System Clock Input
async_reset_i : in std_logic; -- Reset switch on board
-- HDMI In/Rx
tmds_rx_clk_p_i : in std_logic;
tmds_rx_clk_n_i : in std_logic;
tmds_rx_data_p_i : in std_logic_vector(2 downto 0);
tmds_rx_data_n_i : in std_logic_vector(2 downto 0);
hdmi_rx_hpd_o : out std_logic := '1'; -- HPD must be driven
-- I2C
sda_io : inout std_logic;
scl_io : inout std_logic;
-- HDMI Out/Tx
tmds_tx_clk_p_o : out std_logic;
tmds_tx_clk_n_o : out std_logic;
tmds_tx_data_p_o : out std_logic_vector(2 downto 0);
tmds_tx_data_n_o : out std_logic_vector(2 downto 0);
sw : in std_logic
);
end hdmi_pass_top;
architecture hdmi_pass_top_arc of hdmi_pass_top is
component dvi2rgb_0
port (
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
RefClk : in std_logic;
aRst : in std_logic;
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic;
aPixelClkLckd : out std_logic;
SDA_I : in std_logic;
SDA_O : out std_logic;
SDA_T : out std_logic;
SCL_I : in std_logic;
SCL_O : out std_logic;
SCL_T : out std_logic;
pRst : in std_logic
);
end component;
component rgb2dvi_0
PORT (
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
aRst : in std_logic;
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic
);
end component;
component clk_wiz_0
port
(-- Clock in ports
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic;
clk_in1 : in std_logic
);
end component;
signal vid_pData : std_logic_vector(23 downto 0);
signal vid_pVDE : std_logic;
signal vid_pHSync : std_logic;
signal vid_pVSync : std_logic;
signal pixelclk : std_logic;
signal locked : std_logic;
signal clk_200M : std_logic;
signal pixel_clk_sync_rst : std_logic;
signal sda_i : std_logic;
signal sda_o : std_logic;
signal sda_t : std_logic;
signal scl_i : std_logic;
signal scl_o : std_logic;
signal scl_t : std_logic;
begin
clkwiz_inst : clk_wiz_0
port map (
-- Clock out ports
clk_out1 => clk_200M,
-- Status and control signals
reset => async_reset_i,
locked => locked,
-- Clock in ports
clk_in1 => sysclk_i
);
dvi2rgb_inst : dvi2rgb_0
port map (
TMDS_Clk_p => tmds_rx_clk_p_i,
TMDS_Clk_n => tmds_rx_clk_n_i,
TMDS_Data_p => tmds_rx_data_p_i,
TMDS_Data_n => tmds_rx_data_n_i,
RefClk => clk_200M,
aRst => async_reset_i, --Active high asynchronous RefClk reset
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk,
aPixelClkLckd => open, --
SDA_I => sda_i,
SDA_O => sda_o,
SDA_T => sda_t,
SCL_I => scl_i,
SCL_O => scl_o,
SCL_T => scl_t,
pRst => '0' -- Active high PixelClk synchronous reset
);
SDA_IOBUF_inst: IOBUF
generic map(
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map(
O => sda_i, -- Buffer output
IO => sda_io, -- Buffer inout port(connect directly to top-level port)
I => sda_o, -- Bufferinput
T => sda_t -- 3-state enable input,high=input,low=output
);
SCL_IOBUF_inst: IOBUF
generic map(
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map(
O => scl_i, -- Buffer output
IO => scl_io, -- Buffer inout port(connect directly to top-level port)
I => scl_o, -- Buffer input
T => scl_t -- 3-state enable input,high=input,low=output
);
rgb2dvi_inst : rgb2dvi_0
port map (
TMDS_Clk_p => tmds_tx_clk_p_o,
TMDS_Clk_n => tmds_tx_clk_n_o,
TMDS_Data_p => tmds_tx_data_p_o,
TMDS_Data_n => tmds_tx_data_n_o,
aRst => async_reset_i,
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk
);
end hdmi_pass_top_arc;
编辑：将我的if语句更改为
vid_pData(7 downto 0) <= "00000000" when sw = '0';
并且它消除了错误，但是实现失败。失败是：
[[DRC MDRV-1]多驱动程序网：网络dvi2rgb_inst / U0 / GenerateBUFG.ResyncToBUFG_X / vid_pData [0]有多个驱动程序：vid_pData_reg [0] / Q，和dvi2rgb_inst / U0 / GenerateBUFG.ResyncToBUFG_X / poData_reg [0] / Q。
您不是在编写软件，而是在设计硬件。您的额外代码驱动信号vid_pData。因此，dvi2rgb_0分量也是如此。因此，您在该信号上有两个驱动程序。换句话说，就是短路。
[此外，如果vid_pData不等于sw，则您不会说'0'应该取什么值。因此，您将在硬件中遇到闩锁。 （Google“推断出闩锁”。）
您需要一个新信号，例如：
signal vid_pData_new : std_logic_vector(23 downto 0);
然后您需要为sw等于'0'和'1'分配一个值，否则将得到一个锁存器：
vid_pData_new(7 downto 0) <= vid_pData(23 downto 8) & "00000000" when sw = '0' else vid_pData;
&运算符是concatenation运算符。最后，您需要使用新信号来驱动组件rgb2dvi_0：
rgb2dvi_inst : rgb2dvi_0
port map (
TMDS_Clk_p => tmds_tx_clk_p_o,
TMDS_Clk_n => tmds_tx_clk_n_o,
TMDS_Data_p => tmds_tx_data_p_o,
TMDS_Data_n => tmds_tx_data_n_o,
aRst => async_reset_i,
vid_pData => vid_pData_new, -- <-----------------
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk
);
您能看到这里做了什么吗？我们插入了一块新硬件来驱动新信号vid_pData_new，并为sw的两个可能值指定了其值。我们必须执行此操作，否则我们将获得闩锁。我们正在设计硬件，not编写软件。