我一直在尝试适合以下情况的FSM模型的Verilog代码,但是当我使用ModelSim进行测试时,输出(
count
)无法显示我需要的正确输出。
这是我得到的模拟结果:
我写的代码如下:
module fsmkey (
input clock,
input reset,
input key,
output reg [2:0] count);
parameter [2:0]
idle= 3'b000,
Key0 = 3'b000,
Key1 = 3'b001,
Key2 = 3'b010,
Key3 = 3'b011,
Key4 = 3'b100,
Key5 = 3'b101,
Key6 = 3'b110,
Key7 = 3'b111;
reg [1:0] state;
reg [1:0] nxt_state;
always @ (posedge clock or posedge reset)
begin
if (reset) begin
state = Key0;
count = 3'b000;
end
else begin
state = nxt_state;
end
case (state)
Key0:
begin
if (count == 3'b000)
begin
count = 3'b000;
nxt_state = Key0;
end
end
Key1:
begin
if (count == 3'b001)
begin
count = 3'b000;
nxt_state = Key1;
end
else
begin
count = count + 1;
nxt_state = Key1;
end
end
Key2:
begin
if (count == 3'b010)
begin
count = 3'b000;
nxt_state = Key2;
end
else
begin
count = count + 1;
nxt_state = Key2;
end
end
Key3:
begin
if (count == 3'b011)
begin
count = 3'b000;
nxt_state = Key3;
end
else
begin
count = count + 1;
nxt_state = Key3;
end
end
Key4:
begin
if (count == 3'b100)
begin
count = 3'b000;
nxt_state = Key4;
end
else
begin
count = count + 1;
nxt_state = Key4;
end
end
Key5:
begin
if (count == 3'b101)
begin
count = 3'b000;
nxt_state = Key5;
end
else
begin
count = count + 1;
nxt_state = Key5;
end
end
Key6:
begin
if (count == 3'b110)
begin
count = 3'b000;
nxt_state = Key6;
end
else
begin
count = count + 1;
nxt_state = Key6;
end
end
Key7:
begin
if (count == 3'b111)
begin
count = 3'b000;
nxt_state = Key7;
end
else
begin
count = count + 1;
nxt_state = Key7;
end
end
default: nxt_state = idle;
endcase
end
endmodule
以下是测试平台:
module fsmkey_testbench();
reg clock = 0;
reg reset = 1;
reg key;
wire [2:0] count;
// Instantiate the fsmkey module
fsmkey dut (
.clock(clock),
.reset(reset),
.key(key),
.count(count)
);
// Clock generation
always #5 clock = ~clock; // Toggle clock every 5 time units
initial begin
// Reset the unit
reset = 0;
// Simulate key presses
key = 3'b000;
#10 key = 3'b001; // Press Key0
#10 key = 0;
key = 3'b001;
#10 key = 3'b001; // Press Key1
#10 key = 0;
key = 3'b000;
#10 key = 3'b001; // Press Key0
#10 key = 0;
key = 3'b001;
#10 key = 3'b001; // Press Key1
#10 key = 0;
// Continue simulating key presses for other keys as needed...
$stop; // Stop simulation
end
// Display count value
always @(posedge clock) begin
$display("Count = %b", count);
end
endmodule
我找不到影响我的模拟的部分。结果应该遵循上面的 FSM 模型,计数显示结果
您看到
count
= x(未知),因为您没有在测试台中正确重置设计。您在时间 0 时将 reset
正确初始化为 1,但随后也在时间 0 立即将其设置为 0。您需要添加一些延迟。
变化:
reset = 0;
至:
#20 reset = 0;
这会导致
count
被知晓 (0)。
但是,由于 FSM 中的错误,
count
仍然为 0。您将 FSM 重置为状态 Key0
,但随后您无法提供离开该状态的方法。