VHDL错误案例语句的编译问题

Question

我创建了一个项目，但我无法修复它
首先使用图 3 中描述的接口实现图 4 中描述的代码锁的简单版本。使用三进程模板为代码锁实现状态寄存器、下一状态和输出过程。 “sync”在文件中提供，应该在为 code_lock_simple 实现 VHDL ibd 时实例化。同步块的目的是提供一个信号，指示输入信号的上升沿或下降沿。该信号将与 clk 信号同步。 b) 为您的设计创建一个功能仿真，就像您对 Mee-Moo 状态机所做的那样。状态变化是否按预期发生？将仿真波形添加到您的日志中。 c) 创建一个测试器并在 DE2 板上测试您的设计，界面如图 5

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;

entity code_lock_simple is
    port(
            clk : in std_logic;
            reset : in std_logic;
            code : in std_logic_vector(3 downto 0);
            enter : in std_logic;
            -- Lock output
            lock : out std_logic
            );
            
end code_lock_simple;

architecture Behavioral of code_lock_simple is

        type state_type is (Unlocked, Idle, Ev_code1, Get_code2, Ev_code2, Wrong_code, Perm_locked); 
        
        signal present_state, next_state : state_type; 
        
    begin
    state_reg : process (clk, reset)
    begin
        if rising_edge(clk) then
            if reset = '0' then 
                present_state <= Idle;
            else
                present_state <= next_state; 
            end if;
        end if;
    end process; 
    
    outputs : process (present_state, enter, code)
        constant code1 : std_logic_vector(3 downto 0) := "1111";
        constant code2 : std_logic_vector(3 downto 0) := "0000";
        
begin
case present_state is 

     when Idle =>
         if enter = '1' then 
        lock <= '1'; 
      end if; 
    
    when ev_code1 =>
        if enter = '1' and code = code1 then
            lock <= '1';
        elsif enter = '1' and code /= code1 then 
            lock <= '1';
        end if; 
        
    when get_code2 => 
        if enter ='1' then 
            lock <= '1'; 
        end if; 
    
    when ev_code2 => 
        if enter = '1' and code /= code2 then
            lock <= '1';
        elsif enter = '1' and code = code2 then
            lock <= '1'; 
        end if; 
    
    when unlocked => lock <= '0'; 
        if enter = '1' then
            lock <= '1';
        end if;
    end case; 
end process; 

  

                 
        
            
-- NEXT STATE PROCESS
    

------ Hardwirede koder til kodelåsen
 nxt_state : process (present_state, code, enter) 

    constant code1 : std_logic_vector := "1100"; 
    constant code2 : std_logic_vector := "1110";
    
     begin
    
        next_state <= present_state; 
        
        
        case present_state is 
            
            when Idle =>
                if enter = '1' then 
                    next_state <= ev_code1;
                end if; 
            
            when ev_code1 =>
                    if enter = '1' and code = code1 then
                    next_state <= ev_code2;
                    elsif enter = '1' and code /= code1 then 
                        next_state <= Idle; 
                    end if;
            
            when get_code2 =>
                if enter = '1' then 
                    next_state <= ev_code2; 
                end if;
                
            when ev_code2 => 
                if enter = '1' and code /= code2 then 
                    next_state <= Idle; 
                    
                elsif enter = '1' and code = code2 then 
                    next_state <= unlocked; 
                end if; 
            
            when unlocked => lock <= '0'; 
                if enter = '1' then 
                    next_state <= Idle; 
                end if;     
            
            when others =>
                next_state <= Idle; 
        end case;
    end process; 
end; 

我在网上收到这个错误
错误 (10313)：code_lock_simple.vhd(41) 处的 VHDL Case 语句错误：Case 语句选择必须涵盖表达式的所有可能值

Answer 1

我的 VHDL 有点生疏，但这个错误指向你的案例陈述没有涵盖你在这一行中为“state_type”信号定义的每个状态：

type state_type is (Unlocked, Idle, Ev_code1, Get_code2, Ev_code2, Wrong_code, Perm_locked);

要解决此问题，您需要为 Unlocked、Get_code1、Wrong_Code 和 Perm_locked 添加案例。

您需要在案例陈述的两个实例中都涵盖这一点。