使用时钟的边沿触发进行计时

问题描述 投票:0回答:1

假设我有如下代码:

always @(clock)
begin
  if (condition is met)
     a <= 0
  else if (another condition is met)
     b <= 0
end

我希望在时钟的摆位处<= 0,并且在时钟的忽略位置处b <= 0。我该如何指定?

我现在正在做的是...

always @(clock)
begin
   if (condition is met)
      @(posedge clock) a <= 0
   else if (another condition is met)
      @(negedge clock) b <= 0
end
verilog clock timing
1个回答
3
投票

使用两个always块。一个用于posedge,另一个用于negedge

always @(posedge clock) begin
  if (condition is met)
     a <= 0;
end
always @(negedge clock) begin
  if (!(condition is met) && (another condition is met))
     b <= 0;
end
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