VHDL - 行为正常，Post Route有问题

Question

我是StackOverflow的新手，我很抱歉最终出现错误。 我正在使用VHDL，我遇到了Post-Place＆Route的问题。虽然行为正常，但是Post-Place＆Route存在问题，结果始终保持不变。

entity step1 is
  port (   d: in std_logic_vector (0 to 5);
        clk : in std_logic;
            RESET: in std_logic;
        q: out std_logic_vector (0 to 5)
         );
end step1;

architecture Behavioral of step1 is

begin
  ff: process (clk)
  begin
      if (clk'event and clk='1') then
        if (RESET = '1') then
          q <= "000000";
          else
          q <= d;
          end if;
    end if;
    end process;
end Behavioral;

我在这里放置代码。它应该是我用来制作流水线架构的触发器D. 谢谢你的回复，请原谅我有任何错误。 这是测试台：

entity test_step1 is
end test_step1
ARCHITECTURE behavior OF test_step1 IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT step1
PORT(
     input : IN  std_logic_vector(0 to 5);
     clk : IN  std_logic;
     RESET : IN  std_logic;
     output : OUT  std_logic_vector(0 to 5)
    );
END COMPONENT;
--Inputs
signal input : std_logic_vector(0 to 5) := (others => '0');
signal clk : std_logic := '0';
signal RESET : std_logic := '0';

--Outputs
signal output : std_logic_vector(0 to 5);

-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: step1 PORT MAP (
      input => input,
      clk => clk,
      RESET => RESET,
      output => output
    );

 -- Clock process definitions
 clk_process :process
 begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
 end process;
 -- Stimulus process
 stim_proc: process 
 begin    
    -- hold reset state for 100 ns.
  RESET <= '1';
    wait for 10 ns;
  RESET <= '0';
  input <= "111111";
    wait for clk_period*10;
  input <= "101010";

  -- insert stimulus here 

  wait;
  end process;

 END;

Answer 1

在互联网上找到的HDL编译器89和648的第一条警告信息是：

警告：HDLCompiler：89 - “my_module”仍然是一个黑盒子，因为它没有绑定实体。

警告：模拟器：648 - “Top_LCD_test.vhd”第35行。实例top_lcd是实体测试平台的非绑定编译体系结构行为

这意味着编译器没有计算与测试平台中使用的组件相对应的任何实体。

在您的情况下，您的实体和组件的端口名称不匹配！

尝试在端口中为组件和实体使用相同的名称：

entity test_step1 is
end test_step1;
ARCHITECTURE behavior OF test_step1 IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT step1
PORT(
     d : IN  std_logic_vector(0 to 5);
     clk : IN  std_logic;
     RESET : IN  std_logic;
     q : OUT  std_logic_vector(0 to 5)
    );
END COMPONENT;
--Inputs
signal input : std_logic_vector(0 to 5) := (others => '0');
signal clk : std_logic := '0';
signal RESET : std_logic := '0';

--Outputs
signal output : std_logic_vector(0 to 5);

-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: step1 PORT MAP (
      d => input,
      clk => clk,
      RESET => RESET,
      q => output
    );

 -- Clock process definitions
 clk_process :process
 begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
 end process;
 -- Stimulus process
 stim_proc: process 
 begin    
    -- hold reset state for 100 ns.
  RESET <= '1';
    wait for 10 ns;
  RESET <= '0';
  input <= "111111";
    wait for clk_period*10;
  input <= "101010";

  -- insert stimulus here 

  wait;
  end process;