实体在用作组件时不起作用

Question

基本上，标题。 我的

Memory

实体在直接使用时可以正常工作，但是当用作组件时它什么也不做，也没有错误。

Memory

：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY Memory IS
  PORT (
    CLK: in std_logic;
    RST : in std_logic;
    WE : in std_logic;
    ADDR : in std_logic_vector(2 downto 0);
    RAM_DATA_BUS : inout std_logic_vector(9 downto 0);
    ROM_DATA_BUS : out std_logic_vector(9 downto 0)
    );
END Memory;


ARCHITECTURE TypeArchitecture OF Memory IS

BEGIN

ROM: process(CLK, RST)
type ram_matrix IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(9 downto 0);
constant rom_data : ram_matrix := ("1100011000", "0110101010", "XX01111001", "1110001111", "0100001101");
begin
    ROM_DATA_BUS <= rom_data(to_integer(unsigned(ADDR)));

end process ROM;

RAM: process(CLK)
variable ram_data : std_logic_vector(9 downto 0) := "UUUUUUUUUU";
begin
    if RST = '1' then
        ram_data := "UUUUUUUUUU";
    elsif WE = '1' then
        ram_data := RAM_DATA_BUS;
    else
        RAM_DATA_BUS <= ram_data;
    end if;
end process RAM;

END TypeArchitecture;

使用组件的实体：

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ExecutionUnit IS
  PORT (
    CLK : in std_logic;
    RST : in std_logic;
    MEM_WE : in std_logic;
    ROM_ADDR : in std_logic_vector(2 downto 0);
    
    RAM_DATA_BUS : inout std_logic_vector(9 downto 0);

    ROM_DATA_BUS : out std_logic_vector(9 downto 0)
    );
END ExecutionUnit;

ARCHITECTURE TypeArchitecture OF ExecutionUnit IS

component Memory is 
    port(
        CLK: in std_logic;
        RST : in std_logic;
        WE : in std_logic;
        ADDR : in std_logic_vector(2 downto 0);
        RAM_DATA_BUS : inout std_logic_vector(9 downto 0);
        ROM_DATA_BUS : out std_logic_vector(9 downto 0)
        
    );
end component;

signal INT_ROM_DATA_BUS : std_logic_vector(9 downto 0);

BEGIN

MEM: Memory port map(
    CLK => CLK,
    RST => RST,
    WE => MEM_WE,
    ADDR => ROM_ADDR,
    RAM_DATA_BUS => RAM_DATA_BUS,
    ROM_DATA_BUS => INT_ROM_DATA_BUS
);

ROM_DATA_BUS <= INT_ROM_DATA_BUS;

END TypeArchitecture;

注意：我使用Logisim Evolution进行模拟。