Verilog仿真滞后

Question

在verilog中，我想在verilog中设计4位二进制编码的十进制（BCD）。但是当我模拟它时，它在增加位时出现滞后。我的代码或我的模拟参数有问题吗？

这也是我的代码。

module top_module(nReset,Clock,Enable,Cout1,Cout10,Cout100);
input nReset,Clock,Enable;
output [3:0] Cout1,Cout10,Cout100;
wire [1:0] next;
//In top module,we are trying to connect three bcd counters to create decimal counter(121,342 like that). 
BCD_counter c1(.nRst(nReset),.Clk(Clock),.CntEn(Enable),.Cout(Cout1),.NextEn(next[0]));
BCD_counter c2(.nRst(nReset),.Clk(Clock),.CntEn(next[0]),.Cout(Cout10),.NextEn(next[1]));
BCD_counter c3(.nRst(nReset),.Clk(Clock),.CntEn(next[1]),.Cout(Cout100),.NextEn());

endmodule

module BCD_counter(nRst,Clk,CntEn,Cout,NextEn);
//Define reset,clock and count enable as input wires.
input nRst;
input Clk;
input CntEn;
//Define outputs as reg to run in always block.
output reg [3:0]Cout;
//It enables to run next counter.
output NextEn;
//We define an always block.
always @(posedge Clk,negedge nRst)
    //Implement asyncronous active low reset.
    if(nRst == 0)begin
        Cout <= 0;
    //Increment Cout +1 if its smaller than 9 and Count enable is active.
    end else if(Cout < 9 & CntEn == 1)begin
        Cout <= Cout + 1;
    //If cout is equal to 9,go to next counter and assign cout to 0.
    end else if (Cout == 4'd9)begin
        Cout <= 0;
    end

assign NextEn = (Cout == 4'd9) ? 1 : 0;
endmodule

我尝试了不同的代码，在我朋友的电脑上可以正常工作，但结果在我的电脑上是一样的。