我是第一次编写测试平台,但它不起作用。它适用于仅具有加法和减法的简单 4 位 ALU,处理无符号数,并且上溢/下溢应该引发错误。
我预计 temp_result 会很好地分配给结果,但似乎存在问题。我尝试使用变量、信号,但总是存在一些问题。我认为 temp_result 是罪魁祸首。也许它的调用方式或对结果的赋值是错误的,或者是在代码的错误部分。或者也许是测试平台端口图。 抱歉,这是我第一次问这个问题,我是 VHDL 新手,希望我不会太困惑。
这是主要代码:
entity ALU is
port (
A: in unsigned(3 downto 0);
B: in unsigned(3 downto 0);
result: out unsigned(3 downto 0);
opcode: in bit;
error: out bit
);
end entity ALU;
architecture Behavioral of ALU is
signal temp_result: unsigned(4 downto 0);
begin
process(A, B, opcode)
begin
-- Multiplexer to select result based on opcode
case opcode is
when '0' =>
temp_result <= resize(A, temp_result'length) + resize(B, temp_result'length);
when '1' =>
temp_result <= resize(A, temp_result'length) - resize(B, temp_result'length);
end case;
-- Assign result
result <= temp_result(3 downto 0);
-- Error output
if temp_result(4) = '1' then
error <= '1';
else
error <= '0';
end if;
end process;
end Behavioral;
这是测试台:
entity ALU_Testbench is
end ALU_Testbench;
architecture tb_arch of ALU_Testbench is
-- Signals for testbench
signal A_tb, B_tb: unsigned(3 downto 0);
signal opcode_tb: bit;
signal result_tb: unsigned(3 downto 0);
signal error_tb: bit;
-- Component declaration
component ALU
port (
A: in unsigned(3 downto 0);
B: in unsigned(3 downto 0);
result: out unsigned(3 downto 0);
opcode: in bit;
error: out bit
);
end component;
begin
uut_instance: ALU
port map (
A => A_tb,
B => B_tb,
opcode => opcode_tb,
result => result_tb,
error => error_tb
);
-- Stimulus process
stim_proc: process
begin
-- Addition test
A_tb <= "0011";
B_tb <= "0010";
opcode_tb <= '0';
wait for 10 ns;
-- Subtraction test
A_tb <= "0011";
B_tb <= "0010";
opcode_tb <= '1';
wait for 10 ns;
wait;
end process stim_proc;
end tb_arch;
temp_result 是一个信号,因此当进程终止时它会获取新值。但进程对 temp_result 不敏感(敏感列表(A、B、操作码)中缺失)。因此,进程无法将 temp_result 处的新值分配给 result。因此,要解决您的问题,您必须将 temp_result 添加到敏感度列表中,或将信号 temp_result 更改为进程中声明的变量。变量会立即获取其新值,因此在这种情况下您不必更改敏感度列表。