`include"C:\Users\navan\POSIT_MULTIPLIER\posit_mult.v"
`include"C:\Users\navan\Posit_Adder\posit_adder.v"
`include"C:\Users\navan\my_div\basic_calc.v"
module trial_for_div(in1, in2, chum, start, out, inf, zero, done);
function [31:0] log2;//To know how many bits are required to store any type of data
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 32;//Default word size
parameter Bs = log2(N);//Value is calculated as 5- no of bits required to store word size(32).
parameter es = 3;//For posit format-Max exponent size
input [N-1:0] in1, in2;
input start;
output [N-1:0] out;
output inf, zero;//Exceptions
output done;
wire s1=in1[N-1];
wire s2=in2[N-1];
wire [N-1:0] inv_approx_b=-in2;
wire [N-1:0] inv_approx={!inv_approx_b[N-1],inv_approx_b[N-2:0]};// Initial approximation-Taking inverse and changing sign
wire [N-1:0] err;//For calculating how much is to be added
wire [N-1:0] out_b;
wire [N-1:0] inv_approx_bb;
//Sign, Exponent and Mantissa Computation
wire div_s = s1^s2;//sign for result
genvar NR_ITER;//Used as loop variable-Number of Iterations
parameter max_count=10;//Currently set as 10
// main idea is to perform x[i+1]=x[i]+x[i]*(1-x[i]*D)
//basic_calc will give us "(x[i]*(1-x[i]*D))"
//Finding the inverse
generate
begin
for(NR_ITER=0; NR_ITER!=max_count; NR_ITER=NR_ITER+1 )// all the fields in the for loop should be of atleast one genvars and condition in the loop should be of a constant and genvar
begin
basic_calc #(.N(N),.es(es)) bc(inv_approx, in2, err);//x[i]*(1-x[i]*D) is done here
posit_adder pa(inv_approx,err, ,inv_approx_bb, , , );
assign inv_approx=inv_approx_bb;//this assignment is giving me result as don't cares
//x[i+1]=x[i]+x[i]*(1-x[i]*D) is done here
//Here x[i] is taken as inv_approx
end
assign out_b=inv_approx;
posit_mult #(.N(N),.es(es)) mf(in1, out_b, , out, , , );//This is used to make final multiplication
end
endgenerate
endmodule
我正在上传上面代码中包含的支持模块代码。所有支持模块均已针对各种测试案例进行了测试，并已通过验证。
`timescale 1ns / 1ps `include"C:\Users\navan\POSIT_MULTIPLIER\posit_mult.v" `include"C:\Users\navan\Posit_Adder\posit_adder.v" module basic_calc(x, y, err); parameter N = 32; parameter es = 3; input [N-1:0]x; input [N-1:0]y; output [N-1:0] err; wire [N-1:0] x1; wire [N-1:0] x2; reg [N-1:0] oru = 32'h40000000; posit_mult #(.N(N),.es(es)) m1(x, y, , x1, , , ); wire [N-1:0] x1tmp = -x1; posit_adder #(.N(N),.es(es)) a1(x1tmp, oru, , x2, , , ); posit_mult #(.N(N),.es(es)) m2(x, x2, , err, , , ); endmodule
这是乘法模块。
module posit_mult (in1, in2, start, out, inf, zero, done); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 32; parameter Bs = log2(N); parameter es = 3; input [N-1:0] in1, in2; input start; output [N-1:0] out; output inf, zero; output done; wire start0= start; wire s1 = in1[N-1]; wire s2 = in2[N-1]; wire zero_tmp1 = |in1[N-2:0]; wire zero_tmp2 = |in2[N-2:0]; wire inf1 = in1[N-1] & (~zero_tmp1), inf2 = in2[N-1] & (~zero_tmp2); wire zero1 = ~(in1[N-1] | zero_tmp1), zero2 = ~(in2[N-1] | zero_tmp2); assign inf = inf1 | inf2, zero = zero1 & zero2; //Data Extraction wire rc1, rc2; wire [Bs-1:0] regime1, regime2, Lshift1, Lshift2; wire [es-1:0] e1, e2; wire [N-es-1:0] mant1, mant2; wire [N-1:0] xin1 = s1 ? -in1 : in1; wire [N-1:0] xin2 = s2 ? -in2 : in2; data_extract #(.N(N),.es(es)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1), .Lshift(Lshift1)); data_extract #(.N(N),.es(es)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2), .Lshift(Lshift2)); wire [N-es:0] m1 = {zero_tmp1,mant1}, m2 = {zero_tmp2,mant2}; //Sign, Exponent and Mantissa Computation wire mult_s = s1 ^ s2; wire [2*(N-es)+1:0] mult_m = m1*m2; wire mult_m_ovf = mult_m[2*(N-es)+1]; wire [2*(N-es)+1:0] mult_mN = ~mult_m_ovf ? mult_m << 1'b1 : mult_m; wire [Bs+1:0] r1 = rc1 ? {2'b0,regime1} : -regime1; wire [Bs+1:0] r2 = rc2 ? {2'b0,regime2} : -regime2; wire [Bs+es+1:0] mult_e = {r1, e1} + {r2, e2} + mult_m_ovf; //Exponent and Regime Computation wire [es+Bs:0] mult_eN = mult_e[es+Bs+1] ? -mult_e : mult_e; wire [es-1:0] e_o = (mult_e[es+Bs+1] & |mult_eN[es-1:0]) ? mult_e[es-1:0] : mult_eN[es-1:0]; wire [Bs:0] r_o = (~mult_e[es+Bs+1] || (mult_e[es+Bs+1] & |mult_eN[es-1:0])) ? mult_eN[es+Bs:es] + 1'b1 : mult_eN[es+Bs:es]; //Exponent and Mantissa Packing wire [2*N-1:0]tmp_o = {{N{~mult_e[es+Bs+1]}},mult_e[es+Bs+1],e_o,mult_mN[2*(N-es):N-es+2]}; //Including Regime bits in Exponent-Mantissa Packing wire [2*N-1:0] tmp1_o; DSR_right_N_S #(.N(2*N), .S(Bs+1)) dsr2 (.a(tmp_o), .b(r_o[Bs] ? {Bs{1'b1}} : r_o), .c(tmp1_o)); //Final Output wire [2*N-1:0] tmp1_oN = mult_s ? -tmp1_o : tmp1_o; assign out = inf|zero|(~mult_mN[2*(N-es)+1]) ? {inf,{N-1{1'b0}}} : {mult_s, tmp1_oN[N-1:1]}, done = start0; endmodule module DSR_left_N_S(a,b,c); parameter N=16; parameter S=4; input [N-1:0] a; input [S-1:0] b; output [N-1:0] c; wire [N-1:0] tmp [S-1:0]; assign tmp[0] = b[0] ? a << 7'd1 : a; genvar i; generate for (i=1; i<S; i=i+1)begin:loop_blk assign tmp[i] = b[i] ? tmp[i-1] << 2**i : tmp[i-1]; end endgenerate assign c = tmp[S-1]; endmodule module DSR_right_N_S(a,b,c); parameter N=16; parameter S=4; input [N-1:0] a; input [S-1:0] b; output [N-1:0] c; wire [N-1:0] tmp [S-1:0]; assign tmp[0] = b[0] ? a >> 7'd1 : a; genvar i; generate for (i=1; i<S; i=i+1)begin:loop_blk assign tmp[i] = b[i] ? tmp[i-1] >> 2**i : tmp[i-1]; end endgenerate assign c = tmp[S-1]; endmodule module LOD_N (in, out); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 64; parameter S = log2(N); input [N-1:0] in; output [S-1:0] out; wire vld; LOD #(.N(N)) l1 (in, out, vld); endmodule module LOD (in, out, vld); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 64; parameter S = log2(N); input [N-1:0] in; output [S-1:0] out; output vld; generate if (N == 2) begin assign vld = |in; assign out = ~in[1] & in[0]; end else if (N & (N-1)) LOD #(1<<S) LOD ({1<<S {1'b0}} | in,out,vld); else begin wire [S-2:0] out_l, out_h; wire out_vl, out_vh; LOD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl); LOD #(N>>1) h(in[N-1:N>>1],out_h,out_vh); assign vld = out_vl | out_vh; assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l}; end endgenerate endmodule module LZD_N (in, out); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 64; parameter S = log2(N); input [N-1:0] in; output [S-1:0] out; wire vld; LZD #(.N(N)) l1 (in, out, vld); endmodule module LZD (in, out, vld); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 64; parameter S = log2(N); input [N-1:0] in; output [S-1:0] out; output vld; generate if (N == 2) begin assign vld = ~∈ assign out = in[1] & ~in[0]; end else if (N & (N-1)) LZD #(1<<S) LZD ({1<<S {1'b0}} | in,out,vld); else begin wire [S-2:0] out_l; wire [S-2:0] out_h; wire out_vl, out_vh; LZD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl); LZD #(N>>1) h(in[N-1:N>>1],out_h,out_vh); assign vld = out_vl | out_vh; assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l}; end endgenerate endmodule module data_extract(in, rc, regime, exp, mant, Lshift); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N=16; parameter Bs=log2(N); parameter es = 2; input [N-1:0] in; output rc; output [Bs-1:0] regime, Lshift; output [es-1:0] exp; output [N-es-1:0] mant; wire [N-1:0] xin = in; assign rc = xin[N-2]; wire [Bs-1:0] k0, k1; LOD_N #(.N(N)) xinst_k0(.in({xin[N-2:0],1'b0}), .out(k0)); LZD_N #(.N(N)) xinst_k1(.in({xin[N-3:0],2'b0}), .out(k1)); assign regime = xin[N-2] ? k1 : k0; assign Lshift = xin[N-2] ? k1+1 : k0; wire [N-1:0] xin_tmp; DSR_left_N_S #(.N(N), .S(Bs)) ls (.a({xin[N-3:0],2'b0}),.b(Lshift),.c(xin_tmp)); assign exp= xin_tmp[N-1:N-es]; assign mant= xin_tmp[N-es-1:0]; endmodule
这是附加模块。
function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 32; //Posit Word Size parameter Bs = log2(N); parameter es = 3; //Posit Exponent Size input [N-1:0] in1, in2; input start; output [N-1:0] out; output inf, zero; output done; wire start0= start; wire s1 = in1[N-1]; wire s2 = in2[N-1]; wire zero_tmp1 = |in1[N-2:0]; wire zero_tmp2 = |in2[N-2:0]; wire inf1 = in1[N-1] & (~zero_tmp1), inf2 = in2[N-1] & (~zero_tmp2); wire zero1 = ~(in1[N-1] | zero_tmp1), zero2 = ~(in2[N-1] | zero_tmp2); assign inf = inf1 | inf2, zero = zero1 & zero2; //Data Extraction wire rc1, rc2; wire [Bs-1:0] regime1, regime2, Lshift1, Lshift2; wire [es-1:0] e1, e2; wire [N-es-1:0] mant1, mant2; wire [N-1:0] xin1 = s1 ? -in1 : in1; wire [N-1:0] xin2 = s2 ? -in2 : in2; data_extract #(.N(N),.es(es)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1), .Lshift(Lshift1)); data_extract #(.N(N),.es(es)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2), .Lshift(Lshift2)); wire [N-es:0] m1 = {zero_tmp1,mant1}, m2 = {zero_tmp2,mant2}; //Large Checking and Assignment wire in1_gt_in2 = xin1[N-2:0] >= xin2[N-2:0] ? 1'b1 : 1'b0; wire ls = in1_gt_in2 ? s1 : s2; wire op = s1 ~^ s2; wire lrc = in1_gt_in2 ? rc1 : rc2; wire src = in1_gt_in2 ? rc2 : rc1; wire [Bs-1:0] lr = in1_gt_in2 ? regime1 : regime2; wire [Bs-1:0] sr = in1_gt_in2 ? regime2 : regime1; wire [es-1:0] le = in1_gt_in2 ? e1 : e2; wire [es-1:0] se = in1_gt_in2 ? e2 : e1; wire [N-es:0] lm = in1_gt_in2 ? m1 : m2; wire [N-es:0] sm = in1_gt_in2 ? m2 : m1; //Exponent Difference: Lower Mantissa Right Shift Amount wire [Bs:0] r_diff11, r_diff12, r_diff2; sub_N #(.N(Bs)) uut_sub1 (lr, sr, r_diff11); add_N #(.N(Bs)) uut_add1 (lr, sr, r_diff12); sub_N #(.N(Bs)) uut_sub2 (sr, lr, r_diff2); wire [Bs:0] r_diff = lrc ? (src ? r_diff11 : r_diff12) : r_diff2; wire [es+Bs+1:0] diff; sub_N #(.N(es+Bs+1)) uut_sub_diff ({r_diff,le}, {{Bs+1{1'b0}},se}, diff); wire [Bs-1:0] exp_diff = (|diff[es+Bs:Bs]) ? {Bs{1'b1}} : diff[Bs-1:0]; //DSR Right Shifting of Small Mantissa wire [N-1:0] DSR_right_in; generate if (es >= 2) assign DSR_right_in = {sm,{es-1{1'b0}}}; else assign DSR_right_in = sm; endgenerate wire [N-1:0] DSR_right_out; wire [Bs-1:0] DSR_e_diff = exp_diff; DSR_right_N_S #(.N(N), .S(Bs)) dsr1(.a(DSR_right_in), .b(DSR_e_diff), .c(DSR_right_out)); //Mantissa Addition wire [N-1:0] add_m_in1; generate if (es >= 2) assign add_m_in1 = {lm,{es-1{1'b0}}}; else assign add_m_in1 = lm; endgenerate wire [N:0] add_m1, add_m2; add_N #(.N(N)) uut_add_m1 (add_m_in1, DSR_right_out, add_m1); sub_N #(.N(N)) uut_sub_m2 (add_m_in1, DSR_right_out, add_m2); wire [N:0] add_m = op ? add_m1 : add_m2; wire [1:0] mant_ovf = add_m[N:N-1]; //LOD of mantissa addition result wire [N-1:0] LOD_in = {(add_m[N] | add_m[N-1]), add_m[N-2:0]}; wire [Bs-1:0] left_shift; LOD_N #(.N(N)) l2(.in(LOD_in), .out(left_shift)); //DSR Left Shifting of mantissa result wire [N-1:0] DSR_left_out_t; DSR_left_N_S #(.N(N), .S(Bs)) dsl1(.a(add_m[N:1]), .b(left_shift), .c(DSR_left_out_t)); wire [N-1:0] DSR_left_out = DSR_left_out_t[N-1] ? DSR_left_out_t[N-1:0] : {DSR_left_out_t[N-2:0],1'b0}; //Exponent and Regime Computation wire [Bs:0] lr_N = lrc ? {1'b0,lr} : -{1'b0,lr}; wire [es+Bs+1:0] le_o_tmp, le_o; sub_N #(.N(es+Bs+1)) sub3 ({lr_N,le}, {{es+1{1'b0}},left_shift}, le_o_tmp); add_mantovf #(es+Bs+1) uut_add_mantovf (le_o_tmp, mant_ovf[1], le_o); wire [es+Bs:0] le_oN = le_o[es+Bs] ? -le_o : le_o; wire [es-1:0] e_o = (le_o[es+Bs] & |le_oN[es-1:0]) ? le_o[es-1:0] : le_oN[es-1:0]; wire [Bs-1:0] r_o = (~le_o[es+Bs] || (le_o[es+Bs] & |le_oN[es-1:0])) ? le_oN[es+Bs-1:es] + 1'b1 : le_oN[es+Bs-1:es]; //Exponent and Mantissa Packing wire [2*N-1:0]tmp_o = { {N{~le_o[es+Bs]}}, le_o[es+Bs], e_o, DSR_left_out[N-2:es]}; wire [2*N-1:0] tmp1_o; DSR_right_N_S #(.N(2*N), .S(Bs)) dsr2 (.a(tmp_o), .b(r_o), .c(tmp1_o)); //Final Output wire [2*N-1:0] tmp1_oN = ls ? -tmp1_o : tmp1_o; assign out = inf|zero|(~DSR_left_out[N-1]) ? {inf,{N-1{1'b0}}} : {ls, tmp1_oN[N-1:1]}, done = start0; endmodule module data_extract(in, rc, regime, exp, mant, Lshift); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N=16; parameter Bs=log2(N); parameter es = 2; input [N-1:0] in; output rc; output [Bs-1:0] regime, Lshift; output [es-1:0] exp; output [N-es-1:0] mant; wire [N-1:0] xin = in; assign rc = xin[N-2]; wire [Bs-1:0] k0, k1; LOD_N #(.N(N)) xinst_k0(.in({xin[N-2:0],1'b0}), .out(k0)); LZD_N #(.N(N)) xinst_k1(.in({xin[N-3:0],2'b0}), .out(k1)); assign regime = xin[N-2] ? k1 : k0; assign Lshift = xin[N-2] ? k1+1 : k0; wire [N-1:0] xin_tmp; DSR_left_N_S #(.N(N), .S(Bs)) ls (.a({xin[N-3:0],2'b0}),.b(Lshift),.c(xin_tmp)); assign exp= xin_tmp[N-1:N-es]; assign mant= xin_tmp[N-es-1:0]; endmodule module add_mantovf (a,mant_ovf,c); parameter N=32; input [N:0] a; input mant_ovf; output [N:0] c; assign c = a + mant_ovf; endmodule module add_N (a,b,c); input [N-1:0] a; input [N-1:0] b; output [N:0] c; parameter N=32; wire [N:0] w_C; wire [N-1:0] w_G, w_P, w_SUM; // Create the Full Adders genvar ii; generate for (ii=0; ii<N; ii=ii+1) begin full_adder full_adder_inst ( .i_bit1(a[ii]), .i_bit2(b[ii]), .i_carry(w_C[ii]), .o_sum(w_SUM[ii]), .o_carry() ); end endgenerate // Create the Generate (G) Terms: Gi=Ai*Bi // Create the Propagate Terms: Pi=Ai+Bi // Create the Carry Terms: genvar jj; generate for (jj=0; jj<N; jj=jj+1) begin assign w_G[jj] = a[jj] & b[jj]; assign w_P[jj] = a[jj] | b[jj]; assign w_C[jj+1] = w_G[jj] | (w_P[jj] & w_C[jj]); end endgenerate assign w_C[0] = 1'b0; // no carry input on first adder assign c = {w_C[N], w_SUM}; // Verilog Concatenation endmodule // cla_para //FULLADDER module full_adder ( i_bit1, i_bit2, i_carry, o_sum, o_carry ); input i_bit1; input i_bit2; input i_carry; output o_sum; output o_carry; wire w_WIRE_1; wire w_WIRE_2; wire w_WIRE_3; assign w_WIRE_1 = i_bit1 ^ i_bit2; assign w_WIRE_2 = w_WIRE_1 & i_carry; assign w_WIRE_3 = i_bit1 & i_bit2; assign o_sum = w_WIRE_1 ^ i_carry; assign o_carry = w_WIRE_2 | w_WIRE_3; // FYI: Code above using wires will produce the same results as: // assign o_sum = i_bit1 ^ i_bit2 ^ i_carry; // assign o_carry = (i_bit1 ^ i_bit2) & i_carry) | (i_bit1 & i_bit2); // Wires are just used to be explicit. endmodule // full_adder module LZD_N (in, out); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 64; parameter S = log2(N); input [N-1:0] in; output [S-1:0] out; wire vld; LZD #(.N(N)) l1 (in, out, vld); endmodule module LZD (in, out, vld); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 64; parameter S = log2(N); input [N-1:0] in; output [S-1:0] out; output vld; generate if (N == 2) begin assign vld = ~∈ assign out = in[1] & ~in[0]; end else if (N & (N-1)) LZD #(1<<S) LZD ({1<<S {1'b0}} | in,out,vld); else begin wire [S-2:0] out_l; wire [S-2:0] out_h; wire out_vl, out_vh; LZD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl); LZD #(N>>1) h(in[N-1:N>>1],out_h,out_vh); assign vld = out_vl | out_vh; assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l}; end endgenerate endmodule module LOD_N (in, out); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 64; parameter S = log2(N); input [N-1:0] in; output [S-1:0] out; wire vld; LOD #(.N(N)) l1 (in, out, vld); endmodule module LOD (in, out, vld); function [31:0] log2; input reg [31:0] value; begin value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1; end endfunction parameter N = 64; parameter S = log2(N); input [N-1:0] in; output [S-1:0] out; output vld; generate if (N == 2) begin assign vld = |in; assign out = ~in[1] & in[0]; end else if (N & (N-1)) LOD #(1<<S) LOD ({1<<S {1'b0}} | in,out,vld); else begin wire [S-2:0] out_l, out_h; wire out_vl, out_vh; LOD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl); LOD #(N>>1) h(in[N-1:N>>1],out_h,out_vh); assign vld = out_vl | out_vh; assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l}; end endgenerate endmodule module DSR_right_N_S(a,b,c); parameter N=16; parameter S=4; input [N-1:0] a; input [S-1:0] b; output [N-1:0] c; wire [N-1:0] tmp [S-1:0]; assign tmp[0] = b[0] ? a >> 7'd1 : a; genvar i; generate for (i=1; i<S; i=i+1)begin:loop_blk assign tmp[i] = b[i] ? tmp[i-1] >> 2**i : tmp[i-1]; end endgenerate assign c = tmp[S-1]; endmodule module DSR_left_N_S(a,b,c); parameter N=16; parameter S=4; input [N-1:0] a; input [S-1:0] b; output [N-1:0] c; wire [N-1:0] tmp [S-1:0]; assign tmp[0] = b[0] ? a << 7'd1 : a; genvar i; generate for (i=1; i<S; i=i+1)begin:loop_blk assign tmp[i] = b[i] ? tmp[i-1] << 2**i : tmp[i-1]; end endgenerate assign c = tmp[S-1]; endmodule module sub_N (a,b,c); parameter N=10; input [N-1:0] a,b; output [N:0] c; assign c = {1'b0,a} - {1'b0,b}; endmodule
inv_approx，inv_approx_bb，err等具有多个冲突的驱动程序。当网络上有多个活动驱动程序且发生冲突时，结果为X（如果没有活动驱动程序，则结果为Z）每个网络需要由活动驱动程序驱动。在您的情况下，您可能需要一个二维数组，因此每个位都应作为特定的驱动程序。示例：
// ...
wire [N-1:0] inv_approx_b [0:max_count];
wire [N-1:0] inv_approx [0:max_count];
wire [N-1:0] err [0:max_count]; //For calculating how much is to be added
wire [N-1:0] out_b [0:max_count];
wire [N-1:0] inv_approx_bb [0:max_count];
assign inv_approx_b[0]=-in2;
assign inv_approx[0]={!inv_approx_b[N-1],inv_approx_b[N-2:0]};// Initial approximation-Taking inverse and changing sign
// ...
generate
for(NR_ITER=0; NR_ITER<max_count; NR_ITER=NR_ITER+1 )
begin
// ... logic using NR_ITER as index. Ex: err[NR_ITER], err[NR_ITER+1], err[NR_ITER-1]
end
endgenerate
// ...
其他说明：请勿修改输入，并且要注意合成的静态展开要求。仅供参考，Verilog-2005（和SystemVerilog）具有内置的$clog2功能，许多现代合成器都支持该功能。
function [31:0] log2;//To know how many bits are required to store any type of data input [31:0] in; // input cannot be reg type of Verilog (okay with SystemVerilog) reg [31:0] value; reg [7:0] idx; begin value = in-1; log2 = 0; //for (log2=0; value>0; log2=log2+1) // works in simulation but cannot static unroll for synthesis // value = value>>1; for (idx=0; idx<32; idx=idx+1) // can static unroll for synthesis if (value>0) begin value = value>>1; log2 = log2+1; end end endfunction
如果您不需要明确遵循Verilog-1995标准，也可以考虑使用ANSI样式标头（自Verilog-2001开始受支持）。它更易于阅读，而且打字更少。