“赋值语句中的语法l-value”为什么这段代码没有编译?

问题描述 投票:0回答:1
module FiniteStateMachine(output reg [2:0] Count, input clock, reset);
reg[2:0] state, next_state;

parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110, S7 = 3'b111;
always @ (posedge clock, negedge reset)
    if(reset==0) state<=S0;
    else state <= next_state;

always @ (state)
    case(state)
        S0: begin
                Count = S0;
                next_state = S1;
            end
        S1: begin
                Count = S1;
                next_state = S2;
            end
        S2: begin
                Count = S3;
                next_state = S3;
            end
        S3: begin
                Count = S7;
                next_state = S4:
            end
        S4: begin
                Count = S6;
                next_state = S5;
            end
        S5: begin
            Count = S4;
                next_state = S0;
            end
        endcase
endmodule

获取错误“赋值语句l-value中的语法”。对于所有的分配,我也尝试过“<=”而不是“=”,但是我得到了同样的错误。

verilog
1个回答
1
投票

你使用冒号而不是分号。更改:

        next_state = S4:

至:

        next_state = S4;
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