我正在Coursera上做一个名为NandtoTetris的计算机体系结构课程,并且一直在努力学习我的16位CPU设计。该课程使用一种名为HDL的语言,这是一种非常简单的Verilog语言。
我花了这么多时间试图根据下图重复我的CPU设计,我不明白我做错了什么。我尽力代表获取和执行机制。有没有人对如何解决这个问题有任何建议?
以下是设计和控制语法图链接:
这是我的代码如下:
// Put your code here:
// Instruction decoding:from i of “ixxaccccccdddjjj”
// Ainstruction: Instruction is 16-bit value of the constant that should be loaded into the A register
// C-instruction: The a- and c-bits code comp part, d- and j-bits code dest and jump(x-bits are ignored).
Mux16(a=outM, b=instruction, sel=instruction[15], out=aMUX); // 0 for A-instruction or 1 for a C-instruction
Not(in=instruction[15], out=aInst); // assert A instruction with op-code as true
And(a=instruction[15], b=instruction[5], out=cInst); // assert wite-to-A-C-instruction with op code AND d1-bit
Or(a=aInst, b=cInst, out=aMuxload); // assert Ainstruction or wite-to-A-C-instruction is true
ARegister(in=aMUX, load=cInst, out=addressM); // load Ainstruction or wite-to-A-C-instruction
// For C-instruction, a-bit determines if ALU will operate on A register input (0) vs M input (1)
And(a=instruction[15], b=instruction[12], out=Aselector); // assert that c instruction AND a-bit
Mux16(a=addressM, b=inM, sel=Aselector, out=aluMUX); // select A=0 or A=1
ALU(x=DregisterOut, y=aluMUX, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], zr=zr, ng=ng,out=outM);
// The 3 d-bits of “ixxaccccccdddjjj” ALUout determine registers are destinations for for ALUout
// Whenever there is a C-Instruction and d2 (bit 4) is a 1 the D register is loaded
And(a=instruction[15], b=instruction[4], out=writeD); // assert that c instruction AND d2-bit
DRegister(in=outM, load=writeD, out=DregisterOut); // d2 of d-bits for D register destination
// Whenever there is a C-Instruction and d3 (bit 3) is a 1 then writeM (aka RAM[A]) is true
And(a=instruction[15], b=instruction[3], out=writeM); // assert that c instruction AND d3-bit
// Programe counter to fetch next instruction
// PC logic: if (reset==1), then PC = 0
// else:
// load = comparison(instruction jump bits, ALU output zr & ng)
// if load == 1, PC = A
// else: PC ++
And(a=instruction[2], b=ng, out=JLT); // J2 test against ng: out < 0
And(a=instruction[1], b=zr, out=JEQ); // J1 test against zr: out = 0
Or(a=ng, b=zr, out=JGToutMnot)); // J0 test if ng and zr are both zero
Not(in=JGToutMnot, out=JGToutM; // J0 test if ng and zr are both zero
And(a=instruction[0], b=JGToutM, out=JGT);
Or(a=JLT, b=JEQ, out=JLE); // out <= 0
Or(a=JGT, b=JLE, out=JMP); // final jump assertion
And(a=instruction[15], b=JMP, out=PCload); // C instruction AND JMP assert to get the PC load bit
// load in all values into the programme counter if load and reset, otherwise continue increasing
PC(in=addressM, load=PCload, inc=true, reset=reset, out=pc);
在没有为你工作的情况下回答这些问题是很棘手的,从长远来看这对你没有帮助。
一些一般的想法。
潜在问题:我似乎记得使用设计输出(如outM)作为其他东西的输入是一个坏主意。输出应该只是输出。现在您将ALU的输出发送到outM并使用outM作为其他元素的输入。我建议你尝试将ALU输出到一个新的信号“ALUout”,并将其用作其他元素的输入和(通过由writeM控制的多路复用的mux)outM。但请记住,writeM是一个输出!因此,生成writeM的块需要生成自身的副本以用作多路复用器的控件。 FORTUNATELY,一个块可以有多个语句!
例如,现在你正在生成这样的outM(我不会评论它是否错误,我只是用它作为插图):
And(a=instruction[15], b=instruction[3], out=writeM);
您可以像这样创建第二个输出:
And(a=instruction[15], b=instruction[3], out=writeM, out=writeM2)
然后像这样“清理”你的outM:
Mux16(a=false,b=ALUout,sel=writeM2,out=outM);
祝好运!