100 Hz 至 1 Hz Verilog 计数器

Question

module counter(
input wire rst_sel,
input wire clk_in,
output reg clk_out);//// output clock after dividing the input clock by divisor

//version_1
reg[26:0] ctr;
parameter clk_div = 27'd100000000; //100MHz i.e. 100 million cycles in 1 sec


always @(posedge clk_in, negedge rst_sel) 
begin 
    if(~rst_sel)//== 1'b0 or ~
        begin
        ctr <= 'd0;
        clk_out <= 1'd0;
        end
    else
        begin
        ctr  <= ctr + 1'd1;
        if (ctr >= (clk_div-1))
        ctr <= 1'd0;
        clk_out <= (ctr<clk_div/2)?1'b1:1'b0;
        else
            begin
            ctr <= ctr + 1'd1;
            clk_out <= clk_out
            end
        end
    //counting every +ve and -ve edge clock so we get twice the freq so need to divide by 2
    //is ctr < 50 million? yes --> clk_out is 1 (LED ON); no --> clk_out is 0 (LED OFF)
end

endmodule

我这样做对吗？我问过我的老师，他说需要加上除以 2 并且有一个 -1 但我不明白为什么。我的计数器一直计数到 1*e8。有人可以帮忙解释一下吗？