VHDL分配值，取决于下降沿/上升沿

Question

此组件用于检测外部脉冲，并根据特定的输入（cs，选择是否必须依靠上升沿或下降沿，但是显示下一个问题：

Error (10028): Can't resolve multiple constant drivers for net "contadortemp[7]" at ControlLogic.vhd(46)
Error (10029): Constant driver at ControlLogic.vhd(27)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[6]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[5]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[4]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[3]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[2]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[1]" at ControlLogic.vhd(46)
Error (10028): Can't resolve multiple constant drivers for net "contadortemp[0]" at ControlLogic.vhd(46)

问题似乎是将不同的价值观赋予了抗争能力，但是，我不知道为什么。如何更改contadortemp的分配逻辑以获得所需的性能？基于以下事实：根据contadortemp]，这两个选项应在不同的情况下增加相同的信号（cs）

这里是代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Realiza el conteo y lo reinicia si se llegó al top
entity ControlLogic is
--top: Se activa si se llegó al top (viene de MyTimer)
--clk: Reloj proveido por ClkSelect (pulso externo o prescaler) (viene de MyTimer)

--contador: valor del contador (va a MyTimer)
Port(
    cs: in std_logic_vector(2 downto 0);
    top: in std_logic;
    clk: in std_logic;
    contador: out std_logic_vector(7 downto 0)
);
end ControlLogic;

architecture Behavioral of ControlLogic is

signal contadortemp: std_logic_vector (7 downto 0):=(others=>'0');
begin   
    falling_proc : process(clk)
    begin
    if cs = "110" then
        if falling_edge(clk) then
            if (top='0') then
                if contadortemp = "11111111" then
                    contadortemp    <=  (others=>'0');
                else
                    contadortemp    <=  contadortemp + '1';
                end if;
            else
                contadortemp        <=  (others => '0');
            end if;
        end if;
    else
        contadortemp    <= contadortemp;
    end if;
    end process falling_proc;

    rising_proc : process(clk)
    begin
    if cs /= "110" then
        if rising_edge(clk) then
            if (top='0') then
                if contadortemp = "11111111" then
                    contadortemp    <=  (others=>'0');
                else
                    contadortemp    <=  contadortemp + '1';
                end if;
            else
                contadortemp        <=  (others => '0');
            end if;
        end if;
    else
        contadortemp    <= contadortemp;
    end if;
    end process rising_proc;

    contador <= contadortemp;
end Behavioral;
    

此组件用于检测外部脉冲，并根据特定的输入（cs），选择是否必须依靠上升沿或下降沿，但显示下一个问题：错误（10028）：...] >

Answer 1

合并两个进程，因为它们对单个信号敏感（此处为clk）。尝试在过程中使用变量而不是信号。毕竟：认为硬件胜于软件。尝试这样的事情：

architecture Behavioral of ControlLogic is

--signal contadortemp: std_logic_vector (7 downto 0):=(others=>'0');
begin
   falling_and_rising_edge : process(clk)
    variable contadorVar    : std_logic_vector(7 downto 0) := "00000000";
    begin
    if falling_edge(clk) then
        if cs = "110" then
            if (top='0') then
                if contadorVar  = "11111111" then
                    contadorVar     <=  (others=>'0');
                else
                    contadorVar    <=  contadorVar  + '1';
                end if;
            else
                contadorVar       <=  (others => '0');
            end if;
           contador    <= contadorVar;
        end if;
    end if;
        if rising_edge(clk) then
           if cs /= "110" then
             if (top='0') then
                if contadorVar  = "11111111" then
                    contadorVar     <=  (others=>'0');
                else
                    contadorVar    <=  contadorVar  + '1';
                end if;
             else
                contadorVar       <=  (others => '0');
             end if;
        contador    <= contadorVar; 
       end if;
       end if;
    end process falling_and_rising_edge;
end behavioral;