标题说明了一切。我想知道是否有一种方法可以在 SystemVerilog 中连续分配类属性。
大致如下:
class test;
logic test_var [2];
logic foo;
function new();
this.foo = '0;
this.test_var[0] = '0;
assign this.test_var[1] = foo; // continous assignment, however that is possible
endfunction
task updateFoo(input logic temp_foo);
this.foo = temp_foo;
endtask
task readTestVar();
$display("%b and %b", this.test_var[0], this.test_var[1]);
endtask
endclass
initial begin
test ex = new(); // Foo and test_var initialize to zero.
ex.readTestVar(); // Prints "0 and 0"
ex.updateFoo(1); // Foo becomes 1, so does test_var[1]
ex.readTestVar(); // Prints "0 and 1"
end
我搜索了一些测试书籍和互联网,但没有找到任何有用的东西。我想我知道如何解决这个问题,但想知道是否有捷径。
没有。
该代码在我尝试的每个模拟器上都会生成语法错误,并且错误消息非常清晰。
Error-[DTINPCNS] Dynamic type in non-procedural context
"assign this.test_var[1] = this.foo;"
Argument: this.test_var
Class data is not allowed in non-procedural context.
省略
assign
关键字可能就是您正在寻找的:
this.test_var[1] = foo; // continous assignment, however that is possible
使用类时,您必须分叉自己的进程。您不能使用
always
或连续分配。
module top;
class test;
logic test_var [2];
logic foo;
function new();
this.foo = '0;
this.test_var[1] = '0;
fork
forever @foo this.test_var[1] = foo; // continous assignment
join_none
endfunction
function void updateFoo(input logic temp_foo); // Dont use tasks unless they need to consume time
this.foo = temp_foo;
endfunction
function void readTestVar();
$display("%b and %b", this.test_var[0], this.test_var[1]);
endfunction
endclass
test ex; // static variable declaration moved outside of procedural block
initial begin // delays added to prevent race conditions.
ex = new(); // Foo and test_var initialize to zero.
#1 ex.readTestVar(); // Prints "0 and 0"
#1 ex.updateFoo(1); // Foo becomes 1, so does test_var[1]
#1 ex.readTestVar(); // Prints "0 and 1"
end
endmodule