我遇到以下环形振荡器代码的问题:
entity OSCILLATOR is
port( OUTPUT: out std_logic
);
end entity OSCILLATOR;
architecture structural of OSCILLATOR is
component DEL_INV is
generic(D: time);
port( INPUT: in std_logic;
OUTPUT: out std_logic
);
end component DEL_INV;
signal conn: std_logic := '0';
signal conn1: std_logic := '1';
signal conn2: std_logic := '0';
signal de: time := 2 ns;
begin
INV1: DEL_INV generic map(de) port map (conn, conn1);
INV2: DEL_INV generic map(de) port map (conn1, conn2);
INV3: DEL_INV generic map(de) port map (conn2, conn);
OUTPUT <= conn;
end architecture;
特别是,在模拟它时,输出总是U.有人可以解释为什么吗?
分配给信号conn*
的初始值,以确保在模拟中明确定义的起始条件,在'U'
模块上由OUTPUT
驱动的DEL_INV
开始时被覆盖,因此模拟最终卡在所有U
中。
一种解决方案是通过DEL_INV
模块处理初始值,通用允许不同的初始OUTPUT
值,然后在OUTPUT
上使用此初始值,直到该值被明确定义为'0'
或'1'
,可以通过is_x
函数检测到。
更新的代码如下所示。请注意,我在for all: DEL_INV use entity work.DEL_INV(s);
中添加了Renaud Pacalet对not
和逆变器(DEL_INV
)的建议。
library ieee;
use ieee.std_logic_1164.all;
entity DEL_INV is
generic(
D: time;
XOUT: std_logic);
port(
INPUT: in std_logic;
OUTPUT: out std_logic);
end entity DEL_INV;
architecture s of DEL_INV is
signal PRE : std_logic;
begin
PRE <= (not INPUT) after D;
OUTPUT <= XOUT when is_x(PRE) else PRE; -- Drive XOUT if is_x to clean up
end architecture s;
library ieee;
use ieee.std_logic_1164.all;
entity OSCILLATOR is
port(
OUTPUT: out std_logic);
end entity OSCILLATOR;
architecture structural of OSCILLATOR is
component DEL_INV is
generic(
D: time;
XOUT: std_logic);
port(
INPUT: in std_logic;
OUTPUT: out std_logic);
end component DEL_INV;
for all: DEL_INV use entity work.DEL_INV(s);
signal conn : std_logic;
signal conn1 : std_logic;
signal conn2 : std_logic;
constant DE : time := 2 ns;
begin
INV1: DEL_INV generic map(de, '0') port map (conn, conn1);
INV2: DEL_INV generic map(de, '1') port map (conn1, conn2);
INV3: DEL_INV generic map(de, '0') port map (conn2, conn);
OUTPUT <= conn;
end architecture;