BDC 至 7 段解码器 Verilog 代码缺少 VCD 文件

Question

当我将这段代码运行到 EDAplayground 时，它会给我一个错误 强文字 正在查找 VCD 文件... 找不到 *.vcd 文件。 EPWave 将无法打开。您是否使用了 '$dumpfile("dump.vcd"); $dumpvars;'?

//Verilog模块。

模块段7(bcd,seg);

    input [3:0] bcd;
    output [6:0] seg;
    reg [6:0] seg;
always @(bcd)
begin
    case (bcd) //case statement
        0 : seg = 7'b0000001;
        1 : seg = 7'b1001111;
        2 : seg = 7'b0010010;
        3 : seg = 7'b0000110;
        4 : seg = 7'b1001100;
        5 : seg = 7'b0100100;
        6 : seg = 7'b0100000;
        7 : seg = 7'b0001111;
        8 : seg = 7'b0000000;
        9 : seg = 7'b0000100;
        
        default : seg = 7'b1111111; 
    endcase
end

结束模块

测试台：

模块 tb_segment7;

reg [3:0] bcd;
wire [6:0] seg;
integer i;

segment7 uut (.bcd(bcd), .seg(seg));

initial begin
    for(i = 0;i < 16;i = i+1) //run loop for 0 to 15.
    begin
        bcd = i; 
        #10; //wait for 10 ns
    end     
end

结束模块

Answer 1

将下面所示的初始块添加到您的测试平台，以支持波形转储。

module tb_segment7;

  // other stuff

  // add me
  initial
    begin
      $dumpfile("dump.vcd"); 
      $dumpvars;
    end
  
endmodule