为什么不能在VHDL的进程中使用Event?

问题描述 投票:0回答:0

我是 VHDL 的初学者,我正在使用 Spatan6。在下面的代码中,我在 2 个进程中遇到了事件问题。如果 Process1 中的信号发生事件,则该事件不能同时在 Process1 中使用,但如果在 Process2 中使用该信号,那么在 Procees1 中发生的事件将在 Process2 中可用同时 。 问题: “CLOCK”过程中有一个信号作为第 40 行中的“CLK_1SEC”作为计数器状态,每 1s 将在第 48 行中切换。如果计数器计数到 1s,则“CLK_1SEC”将被切换并且“LED”第 49 行中的必须根据“CLK_1SEC”的状态进行更改,但 LED 状态将与“CLK_1SEC”的状态相反。而在“Delay”过程中,“LED_DELAY”状态会根据“CLK_1SEC”的状态发生变化。请帮助我。

----------------------------------------------------------------------------------
  -- Company: 
  -- Engineer: 
  -- 
  -- Create Date:    14:58:59 03/25/2023 
  -- Design Name: 
  -- Module Name:    delay - Behavioral 
  -- Project Name: 
  -- Target Devices: 
  -- Tool versions: 
  -- Description: 
  --
  -- Dependencies: 
  --
  -- Revision: 
  -- Revision 0.01 - File Created
  -- Additional Comments: 
  --
  ----------------------------------------------------------------------------------
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;

  -- Uncomment the following library declaration if using
  -- arithmetic functions with Signed or Unsigned values
  --use IEEE.NUMERIC_STD.ALL;

  -- Uncomment the following library declaration if instantiating
  -- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;

  entity delay is
     Port ( CLKIN : in  STD_LOGIC;                          -- FPGA clock at 50 MHz (20 ns period)
           LED : out  STD_LOGIC;                                -- Image of the clock and 100 ms
           LED_DELAY : out  STD_LOGIC                   -- delayed clock of 1 sec period
           );
  end delay;

  architecture Behavioral of delay is
  signal CLK_1SEC: std_logic :='0';                -- 1 sec period clock
  begin
     Clock: process(CLKIN, CLK_1SEC)               -- 1 sec counter
           constant MAX: integer := 50000000;          -- 50*10^6 * 20 ns = 1000 ms 
           variable iCOUNT: integer := 0;             -- Counter
           begin
              if (iCOUNT = MAX) then
                 iCOUNT := 0;
                 CLK_1SEC <= NOT CLK_1SEC;             -- Makes 1 sec period for 2 alternances
                 LED <= CLK_1SEC;
              elsif (rising_edge(CLKIN)) then
                 iCOUNT := iCOUNT + 1;
              end if;
           end process;

     Delay: process(CLK_1SEC)                                             
     begin
        LED_DELAY <= CLK_1SEC;;
     end process;


  end Behavioral;
process vhdl fpga status xilinx
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