GCD -Verilog中Stein的算法，期待一个陈述

Question

我正在尝试编写 GCD 算法，但它一直给我这样的错误：

在这种情况下，网络不是合法的左值

 module gcd #(parameter GCD_LENGTH = 13) (
   input clk,           // Clock input
   input nrst,          // Reset, active on negative edge
   input [GCD_LENGTH-1:0] in_a, // first gcd input
   input [GCD_LENGTH-1:0] in_b, // second gcd input
   output [GCD_LENGTH-1:0] gcd, // gcd output
   output valid         // Indicator that gcd output is valid
 ); //5+8
 
 // regs
 // reg[12:0] gcd_output = gcd;
 reg[GCD_LENGTH-1:0] a_input  ;
 reg[GCD_LENGTH-1:0] b_input ;
 // reg[12:0] mult_by_two  
 initial begin
 a_input <= in_a;
 b_input <= in_b;
 end
 //a_input <= in_a ;
 // b_input <= in_b ;
 integer  mult_by_two = 0;
 
 always @((a_input != b_input) && (b_input ==0) && (a_input ==0)) //begin
    if ((a_input &1 ==0) && (b_input&1 ==0)) begin
        // both are even
        a_input = a_input << 1;
        b_input = b_input << 1;
        mult_by_two = mult_by_two +1 ;
    end
    else if ((a_input &1 ==1) && (b_input &1 ==1)) begin
        // both are  odd
        b_input = b_input> a_input ? b_input : a_input;        // putting the min in the b reg
        a_input =  b_input>a_input ? b_input - a_input : a_input-b_input; // putting the difference in a reg
    end
    else if ((a_input & 1 == 1) && (b_input & 1 == 0))
        // a is even, b is odd
        a_input = a_input << 1;
    else if ((a_input & 1 == 0) && (b_input & 1 == 1))
        // b is even, a is odd
        b_input = b_input << 1;
   //end
 
   always @(posedge clk or negedge nrst)
    if (!nrst) begin
        gcd     =13'b0;
        valid <=1'b0;
    end
    else if (a_input == b_input) begin
        gcd = a_input << mult_by_two;
        valid <=1'b1;
    end
    else if (a_input ==0) begin
        gcd = b_input << mult_by_two;
        valid <= 1'b1 ;
    end
    else begin
        gcd = a_input << mult_by_two;
        valid <=1'b1 ;
    end 
 endmodule

我不明白为什么我会收到这些错误